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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus32_lit.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_lit  default
 
 
 

 
 
 wb_clk
  
  
  
    
      
        clk
        wb_clk_i
      
    
 
 
 
 wb_reset
  
  
  
    
      
        reset
        wb_rst_i
      
    
 
 
 
 
 
wb
   
   
   little
   8
     
     
 
        
         adr
         
         wb_adr_i
           72
         
       
 
 
        
         wdata
         
         wb_dat_i
           310
         
       
 
 
        
         rdata
         
         wb_dat_o
           310
         
       
 
 
        
         sel
         
         wb_sel_i
           30
         
       
 
 
 
        
         ack
         
         wb_ack_o
         
       
 
 
        
         cyc
         
         wb_cyc_i
         
       
 
 
 
        
         stb
         
         wb_stb_i
         
       
 
 
        
         we
         
         wb_we_i
         
       
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 

  gen_registers
  103.0
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.bus32_lit
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
 
    
      fs-sim
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.bus32_lit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus32_lit_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-syn
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.bus32_lit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus32_lit_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
    
 
 
  
 
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

wb_addr_width8
wb_data_width32
wb_byte_lanes4
PRESCALER_PRESET16'h1234

 
 

 
baud_o
  wire
  out

 
cts_pad_i
  wire
  in

 
dcd_pad_i
  wire
  in

 
dsr_pad_i
  wire
  in

 
dtr_pad_o
  wire
  out

 
int_o
  wire
  out

 
 
ri_pad_i
  wire
  in

 
rts_pad_o
  wire
  out

 
srx_pad_i
  wire
  in

 
stx_pad_o
  wire
  out

 
 
 
 

 

 
 
 


 wb
8

 wb
 0x00
 
  
  mb_microbus
  0x100
  32
 
 
 
   rb_dll_reg
   0x0
   8
   read-only
  
 
 
   tr_reg
   0x0
   8
   write-strobe
  
 
 
 
   ie_dlh_reg
   0x1
   8
   read-only
  
 
 
   ie_reg
   0x1
   4
   write-strobe
  
 
 
 
   dll_reg
   0x0
   8
   write-strobe
  
 
 
 
   dlh_reg
   0x1
   8
   write-strobe
  
 
 
 
 
 
   ii_reg
   0x2
   4
   read-only
  
 
 
   fc_reg
   0x2
   8
   write-only
  
 
 
 
   lc_reg
   0x3
   8
   read-write
  
 
 
   mc_reg
   0x4
   5
   read-write
  
 
 
   ls_reg
   0x5
   8
   read-only
  
 
 
   ms_reg
   0x6
   8
   read-only
  
 
 
   sr_reg
   0x7
   8
   read-write
  
 
 
 
   debug_0_reg
   0x8
   32
   read-only
  
 
 
 
   debug_1_reg
   0xc
   32
   read-only
  
 
 
 
 
 
 
 
  
 
 

 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus32_lit.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_lit default`
41
42
43
44
45
46
47			`wb_clk`
48
49
50
51
52
53			`clk`
54			`wb_clk_i`
55
56
57
58
59
60			`wb_reset`
61
62
63
64
65
66			`reset`
67			`wb_rst_i`
68
69
70
71
72
73
74
75			`wb`
76
77
78			`little`
79			`8`
80
81
82
83
84			`adr`
85
86			`wb_adr_i`
87			`72`
88
89
90
91
92
93			`wdata`
94
95			`wb_dat_i`
96			`310`
97
98
99
100
101
102			`rdata`
103
104			`wb_dat_o`
105			`310`
106
107
108
109
110
111			`sel`
112
113			`wb_sel_i`
114			`30`
115
116
117
118
119
120
121			`ack`
122
123			`wb_ack_o`
124
125
126
127
128
129			`cyc`
130
131			`wb_cyc_i`
132
133
134
135
136
137
138			`stb`
139
140			`wb_stb_i`
141
142
143
144
145
146			`we`
147
148			`wb_we_i`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170			`gen_registers`
171			`103.0`
172			`none`
173			`common`
174			`./tools/regtool/gen_registers`
175
176
177			`bus_intf`
178			`wb`
179
180
181			`dest_dir`
182			`../verilog`
183
184
185
186
187
188
189
190
191			`gen_verilog`
192			`104.0`
193			`none`
194			`common`
195			`./tools/verilog/gen_verilog`
196
197
198			`destination`
199			`top.bus32_lit`
200
201
202			`dest_dir`
203			`../verilog`
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218			`fs-common`
219
220
221
222			`../verilog/top.body`
223			`verilogSourcefragment`
224
225
226
227
228
229
230
231			`fs-sim`
232
233
234			`../verilog/copyright.v`
235			`verilogSourceinclude`
236
237
238
239
240			`../verilog/common/top.bus32_lit`
241			`verilogSourcemodule`
242
243
244
245
246
247			`../verilog/defines`
248			`verilogSourceinclude`
249
250
251
252			`wb`
253			`../verilog/wb_uart16550_bus32_lit_wb`
254			`verilogSourcemodule`
255
256
257
258
259			`raminfr`
260			`../verilog/raminfr`
261			`verilogSourcemodule`
262
263
264
265			`receiver`
266			`../verilog/receiver`
267			`verilogSourcemodule`
268
269
270
271			`regs`
272			`../verilog/regs`
273			`verilogSourcemodule`
274
275
276
277			`rfifo`
278			`../verilog/rfifo`
279			`verilogSourcemodule`
280
281
282
283			`sync_flops`
284			`../verilog/sync_flops`
285			`verilogSourcemodule`
286
287
288
289			`tfifo`
290			`../verilog/tfifo`
291			`verilogSourcemodule`
292
293
294
295			`transmitter`
296			`../verilog/transmitter`
297			`verilogSourcemodule`
298
299
300
301			`wb_fsm`
302			`../verilog/wb_fsm`
303			`verilogSourcemodule`
304
305
306
307
308
309
310
311
312			`fs-syn`
313
314
315			`../verilog/copyright.v`
316			`verilogSourceinclude`
317
318
319
320
321			`../verilog/common/top.bus32_lit`
322			`verilogSourcemodule`
323
324
325
326
327
328			`../verilog/defines`
329			`verilogSourceinclude`
330
331
332
333			`wb`
334			`../verilog/wb_uart16550_bus32_lit_wb`
335			`verilogSourcemodule`
336
337
338
339
340			`raminfr`
341			`../verilog/raminfr`
342			`verilogSourcemodule`
343
344
345
346			`receiver`
347			`../verilog/receiver`
348			`verilogSourcemodule`
349
350
351
352			`regs`
353			`../verilog/regs`
354			`verilogSourcemodule`
355
356
357
358			`rfifo`
359			`../verilog/rfifo`
360			`verilogSourcemodule`
361
362
363
364			`sync_flops`
365			`../verilog/sync_flops`
366			`verilogSourcemodule`
367
368
369
370			`tfifo`
371			`../verilog/tfifo`
372			`verilogSourcemodule`
373
374
375
376			`transmitter`
377			`../verilog/transmitter`
378			`verilogSourcemodule`
379
380
381
382			`wb_fsm`
383			`../verilog/wb_fsm`
384			`verilogSourcemodule`
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402			`verilog`
403
404
405			`spirit:library="Testbench"`
406			`spirit:name="toolflow"`
407			`spirit:version="verilog"/>`
408
409
410
411
412
413
414
415
416			`commoncommon`
417
418			`Verilog`
419
420
421			`fs-common`
422
423
424
425
426
427			`sim:Simulation:`
428
429			`Verilog`
430
431
432			`fs-sim`
433
434
435
436
437			`syn:Synthesis:`
438
439			`Verilog`
440
441
442			`fs-syn`
443
444
445
446
447
448
449			`doc`
450
451
452			`spirit:library="Testbench"`
453			`spirit:name="toolflow"`
454			`spirit:version="documentation"/>`
455
456			`:Documentation:`
457			`Verilog`
458
459
460
461
462
463
464
465
466			`wb_addr_width8`
467			`wb_data_width32`
468			`wb_byte_lanes4`
469			`PRESCALER_PRESET16'h1234`
470
471
472
473
474
475			`baud_o`
476			`wire`
477			`out`
478
479
480			`cts_pad_i`
481			`wire`
482			`in`
483
484
485			`dcd_pad_i`
486			`wire`
487			`in`
488
489
490			`dsr_pad_i`
491			`wire`
492			`in`
493
494
495			`dtr_pad_o`
496			`wire`
497			`out`
498
499
500			`int_o`
501			`wire`
502			`out`
503
504
505
506			`ri_pad_i`
507			`wire`
508			`in`
509
510
511			`rts_pad_o`
512			`wire`
513			`out`
514
515
516			`srx_pad_i`
517			`wire`
518			`in`
519
520
521			`stx_pad_o`
522			`wire`
523			`out`
524
525
526
527
528
529
530
531
532
533
534
535
536
537			`wb`
538			`8`
539
540			`wb`
541			`0x00`
542
543
544			`mb_microbus`
545			`0x100`
546			`32`
547
548
549
550			`rb_dll_reg`
551			`0x0`
552			`8`
553			`read-only`
554
555
556
557			`tr_reg`
558			`0x0`
559			`8`
560			`write-strobe`
561
562
563
564
565			`ie_dlh_reg`
566			`0x1`
567			`8`
568			`read-only`
569
570
571
572			`ie_reg`
573			`0x1`
574			`4`
575			`write-strobe`
576
577
578
579
580			`dll_reg`
581			`0x0`
582			`8`
583			`write-strobe`
584
585
586
587
588			`dlh_reg`
589			`0x1`
590			`8`
591			`write-strobe`
592
593
594
595
596
597
598			`ii_reg`
599			`0x2`
600			`4`
601			`read-only`
602
603
604
605			`fc_reg`
606			`0x2`
607			`8`
608			`write-only`
609
610
611
612
613			`lc_reg`
614			`0x3`
615			`8`
616			`read-write`
617
618
619
620			`mc_reg`
621			`0x4`
622			`5`
623			`read-write`
624
625
626
627			`ls_reg`
628			`0x5`
629			`8`
630			`read-only`
631
632
633
634			`ms_reg`
635			`0x6`
636			`8`
637			`read-only`
638
639
640
641			`sr_reg`
642			`0x7`
643			`8`
644			`read-write`
645
646
647
648
649			`debug_0_reg`
650			`0x8`
651			`32`
652			`read-only`
653
654
655
656
657			`debug_1_reg`
658			`0xc`
659			`32`
660			`read-only`
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679