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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus32_lit.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_lit  default
 
 
 

 
 
 wb_clk
  
  
  
    
      
        clk
        wb_clk_i
      
    
 
 
 
 wb_reset
  
  
  
    
      
        reset
        wb_rst_i
      
    
 
 
 
 
 
wb
   
   
   little
   8
     
     
 
        
         adr
         
         wb_adr_i
           72
         
       
 
 
        
         wdata
         
         wb_dat_i
           310
         
       
 
 
        
         rdata
         
         wb_dat_o
           310
         
       
 
 
        
         sel
         
         wb_sel_i
           30
         
       
 
 
 
        
         ack
         
         wb_ack_o
         
       
 
 
        
         cyc
         
         wb_cyc_i
         
       
 
 
 
        
         stb
         
         wb_stb_i
         
       
 
 
        
         we
         
         wb_we_i
         
       
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_registers
  102.1
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.bus32_lit
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
 
    
      fs-sim
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.bus32_lit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus32_lit_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-syn
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.bus32_lit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus32_lit_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
    
 
 
  
 
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

wb_addr_width8
wb_data_width32
wb_byte_lanes4
PRESCALER_PRESET16'h1234

 
 

 
baud_o
  wire
  out

 
cts_pad_i
  wire
  in

 
dcd_pad_i
  wire
  in

 
dsr_pad_i
  wire
  in

 
dtr_pad_o
  wire
  out

 
int_o
  wire
  out

 
 
ri_pad_i
  wire
  in

 
rts_pad_o
  wire
  out

 
srx_pad_i
  wire
  in

 
stx_pad_o
  wire
  out

 
 
 
 

 

 
 
 


 wb
8

 wb
 0x00
 
  
  mb_microbus
  0x100
  32
 
 
 
   rb_dll_reg
   0x0
   8
   read-only
  
 
 
   tr_reg
   0x0
   8
   write-strobe
  
 
 
 
   ie_dlh_reg
   0x1
   8
   read-only
  
 
 
   ie_reg
   0x1
   4
   write-strobe
  
 
 
 
   dll_reg
   0x0
   8
   write-strobe
  
 
 
 
   dlh_reg
   0x1
   8
   write-strobe
  
 
 
 
 
 
   ii_reg
   0x2
   4
   read-only
  
 
 
   fc_reg
   0x2
   8
   write-only
  
 
 
 
   lc_reg
   0x3
   8
   read-write
  
 
 
   mc_reg
   0x4
   5
   read-write
  
 
 
   ls_reg
   0x5
   8
   read-only
  
 
 
   ms_reg
   0x6
   8
   read-only
  
 
 
   sr_reg
   0x7
   8
   read-write
  
 
 
 
   debug_0_reg
   0x8
   32
   read-only
  
 
 
 
   debug_1_reg
   0xc
   32
   read-only
  
 
 
 
 
 
 
 
  
 
 

 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus32_lit.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_lit default`
41
42
43
44
45
46
47			`wb_clk`
48
49
50
51
52
53			`clk`
54			`wb_clk_i`
55
56
57
58
59
60			`wb_reset`
61
62
63
64
65
66			`reset`
67			`wb_rst_i`
68
69
70
71
72
73
74
75			`wb`
76
77
78			`little`
79			`8`
80
81
82
83
84			`adr`
85
86			`wb_adr_i`
87			`72`
88
89
90
91
92
93			`wdata`
94
95			`wb_dat_i`
96			`310`
97
98
99
100
101
102			`rdata`
103
104			`wb_dat_o`
105			`310`
106
107
108
109
110
111			`sel`
112
113			`wb_sel_i`
114			`30`
115
116
117
118
119
120
121			`ack`
122
123			`wb_ack_o`
124
125
126
127
128
129			`cyc`
130
131			`wb_cyc_i`
132
133
134
135
136
137
138			`stb`
139
140			`wb_stb_i`
141
142
143
144
145
146			`we`
147
148			`wb_we_i`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169	133	jt_eaton
170	131	jt_eaton
171	133	jt_eaton	`elab_verilog`
172			`102.1`
173			`none`
174			`:Simulation:`
175			`./tools/verilog/elab_verilog`
176
177
178			`dest_dir`
179			`io_ports`
180
181
182
183
184
185
186
187
188	131	jt_eaton	`gen_registers`
189	133	jt_eaton	`102.1`
190	131	jt_eaton	`none`
191			`common`
192			`./tools/regtool/gen_registers`
193
194
195			`bus_intf`
196			`wb`
197
198
199			`dest_dir`
200			`../verilog`
201
202
203
204
205
206
207
208
209			`gen_verilog`
210			`104.0`
211			`none`
212			`common`
213			`./tools/verilog/gen_verilog`
214
215
216			`destination`
217			`top.bus32_lit`
218
219
220			`dest_dir`
221			`../verilog`
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236			`fs-common`
237
238
239
240			`../verilog/top.body`
241			`verilogSourcefragment`
242
243
244
245
246
247
248
249			`fs-sim`
250
251
252			`../verilog/copyright.v`
253			`verilogSourceinclude`
254
255
256
257
258			`../verilog/common/top.bus32_lit`
259			`verilogSourcemodule`
260
261
262
263
264
265			`../verilog/defines`
266			`verilogSourceinclude`
267
268
269
270			`wb`
271			`../verilog/wb_uart16550_bus32_lit_wb`
272			`verilogSourcemodule`
273
274
275
276
277			`raminfr`
278			`../verilog/raminfr`
279			`verilogSourcemodule`
280
281
282
283			`receiver`
284			`../verilog/receiver`
285			`verilogSourcemodule`
286
287
288
289			`regs`
290			`../verilog/regs`
291			`verilogSourcemodule`
292
293
294
295			`rfifo`
296			`../verilog/rfifo`
297			`verilogSourcemodule`
298
299
300
301			`sync_flops`
302			`../verilog/sync_flops`
303			`verilogSourcemodule`
304
305
306
307			`tfifo`
308			`../verilog/tfifo`
309			`verilogSourcemodule`
310
311
312
313			`transmitter`
314			`../verilog/transmitter`
315			`verilogSourcemodule`
316
317
318
319			`wb_fsm`
320			`../verilog/wb_fsm`
321			`verilogSourcemodule`
322
323
324
325
326
327
328
329
330			`fs-syn`
331
332
333			`../verilog/copyright.v`
334			`verilogSourceinclude`
335
336
337
338
339			`../verilog/common/top.bus32_lit`
340			`verilogSourcemodule`
341
342
343
344
345
346			`../verilog/defines`
347			`verilogSourceinclude`
348
349
350
351			`wb`
352			`../verilog/wb_uart16550_bus32_lit_wb`
353			`verilogSourcemodule`
354
355
356
357
358			`raminfr`
359			`../verilog/raminfr`
360			`verilogSourcemodule`
361
362
363
364			`receiver`
365			`../verilog/receiver`
366			`verilogSourcemodule`
367
368
369
370			`regs`
371			`../verilog/regs`
372			`verilogSourcemodule`
373
374
375
376			`rfifo`
377			`../verilog/rfifo`
378			`verilogSourcemodule`
379
380
381
382			`sync_flops`
383			`../verilog/sync_flops`
384			`verilogSourcemodule`
385
386
387
388			`tfifo`
389			`../verilog/tfifo`
390			`verilogSourcemodule`
391
392
393
394			`transmitter`
395			`../verilog/transmitter`
396			`verilogSourcemodule`
397
398
399
400			`wb_fsm`
401			`../verilog/wb_fsm`
402			`verilogSourcemodule`
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420			`verilog`
421
422
423			`spirit:library="Testbench"`
424			`spirit:name="toolflow"`
425			`spirit:version="verilog"/>`
426
427
428
429
430
431
432
433
434			`commoncommon`
435
436			`Verilog`
437
438
439			`fs-common`
440
441
442
443
444
445			`sim:Simulation:`
446
447			`Verilog`
448
449
450			`fs-sim`
451
452
453
454
455			`syn:Synthesis:`
456
457			`Verilog`
458
459
460			`fs-syn`
461
462
463
464
465
466
467			`doc`
468
469
470			`spirit:library="Testbench"`
471			`spirit:name="toolflow"`
472			`spirit:version="documentation"/>`
473
474			`:Documentation:`
475			`Verilog`
476
477
478
479
480
481
482
483
484			`wb_addr_width8`
485			`wb_data_width32`
486			`wb_byte_lanes4`
487			`PRESCALER_PRESET16'h1234`
488
489
490
491
492
493			`baud_o`
494			`wire`
495			`out`
496
497
498			`cts_pad_i`
499			`wire`
500			`in`
501
502
503			`dcd_pad_i`
504			`wire`
505			`in`
506
507
508			`dsr_pad_i`
509			`wire`
510			`in`
511
512
513			`dtr_pad_o`
514			`wire`
515			`out`
516
517
518			`int_o`
519			`wire`
520			`out`
521
522
523
524			`ri_pad_i`
525			`wire`
526			`in`
527
528
529			`rts_pad_o`
530			`wire`
531			`out`
532
533
534			`srx_pad_i`
535			`wire`
536			`in`
537
538
539			`stx_pad_o`
540			`wire`
541			`out`
542
543
544
545
546
547
548
549
550
551
552
553
554
555			`wb`
556			`8`
557
558			`wb`
559			`0x00`
560
561
562			`mb_microbus`
563			`0x100`
564			`32`
565
566
567
568			`rb_dll_reg`
569			`0x0`
570			`8`
571			`read-only`
572
573
574
575			`tr_reg`
576			`0x0`
577			`8`
578			`write-strobe`
579
580
581
582
583			`ie_dlh_reg`
584			`0x1`
585			`8`
586			`read-only`
587
588
589
590			`ie_reg`
591			`0x1`
592			`4`
593			`write-strobe`
594
595
596
597
598			`dll_reg`
599			`0x0`
600			`8`
601			`write-strobe`
602
603
604
605
606			`dlh_reg`
607			`0x1`
608			`8`
609			`write-strobe`
610
611
612
613
614
615
616			`ii_reg`
617			`0x2`
618			`4`
619			`read-only`
620
621
622
623			`fc_reg`
624			`0x2`
625			`8`
626			`write-only`
627
628
629
630
631			`lc_reg`
632			`0x3`
633			`8`
634			`read-write`
635
636
637
638			`mc_reg`
639			`0x4`
640			`5`
641			`read-write`
642
643
644
645			`ls_reg`
646			`0x5`
647			`8`
648			`read-only`
649
650
651
652			`ms_reg`
653			`0x6`
654			`8`
655			`read-only`
656
657
658
659			`sr_reg`
660			`0x7`
661			`8`
662			`read-write`
663
664
665
666
667			`debug_0_reg`
668			`0x8`
669			`32`
670			`read-only`
671
672
673
674
675			`debug_1_reg`
676			`0xc`
677			`32`
678			`read-only`
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697