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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus32_lit.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_lit  default
 
 
 

 
 
 wb_clk
  
  
  
    
      
        clk
        wb_clk_i
      
    
 
 
 
 wb_reset
  
  
  
    
      
        reset
        wb_rst_i
      
    
 
 
 
 
 
wb
   
   
   little
   8
     
     
 
        
         adr
         
         wb_adr_i
           72
         
       
 
 
        
         wdata
         
         wb_dat_i
           310
         
       
 
 
        
         rdata
         
         wb_dat_o
           310
         
       
 
 
        
         sel
         
         wb_sel_i
           30
         
       
 
 
 
        
         ack
         
         wb_ack_o
         
       
 
 
        
         cyc
         
         wb_cyc_i
         
       
 
 
 
        
         stb
         
         wb_stb_i
         
       
 
 
        
         we
         
         wb_we_i
         
       
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 
 
 
 
 
 

  gen_registers
  102.1
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      wb_uart16550_bus32_lit
    
  

 
 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
 
    
      fs-sim
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/wb_uart16550_bus32_lit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus32_lit_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-syn
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/wb_uart16550_bus32_lit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus32_lit_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
    
 
 
  
 
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 
 
 

 
baud_o
  wire
  out

 
cts_pad_i
  wire
  in

 
dcd_pad_i
  wire
  in

 
dsr_pad_i
  wire
  in

 
dtr_pad_o
  wire
  out

 
int_o
  wire
  out

 
 
ri_pad_i
  wire
  in

 
rts_pad_o
  wire
  out

 
srx_pad_i
  wire
  in

 
stx_pad_o
  wire
  out

 
 
 
 

 

 
 
 


 wb
8

 wb
 0x00
 
  
  mb_microbus
  0x100
  32
 
 
 
   rb_dll_reg
   0x0
   8
   read-only
  
 
 
   tr_reg
   0x0
   8
   write-strobe
  
 
 
 
   ie_dlh_reg
   0x1
   8
   read-only
  
 
 
   ie_reg
   0x1
   4
   write-strobe
  
 
 
 
   dll_reg
   0x0
   8
   write-strobe
  
 
 
 
   dlh_reg
   0x1
   8
   write-strobe
  
 
 
 
 
 
   ii_reg
   0x2
   4
   read-only
  
 
 
   fc_reg
   0x2
   8
   write-only
  
 
 
 
   lc_reg
   0x3
   8
   read-write
  
 
 
   mc_reg
   0x4
   5
   read-write
  
 
 
   ls_reg
   0x5
   8
   read-only
  
 
 
   ms_reg
   0x6
   8
   read-only
  
 
 
   sr_reg
   0x7
   8
   read-write
  
 
 
 
   debug_0_reg
   0x8
   32
   read-only
  
 
 
 
   debug_1_reg
   0xc
   32
   read-only
  
 
 
 
 
 
 
 
  
 
 

 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus32_lit.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_lit default`
41
42
43
44
45
46
47			`wb_clk`
48
49
50
51
52
53			`clk`
54			`wb_clk_i`
55
56
57
58
59
60			`wb_reset`
61
62
63
64
65
66			`reset`
67			`wb_rst_i`
68
69
70
71
72
73
74
75			`wb`
76
77
78			`little`
79			`8`
80
81
82
83
84			`adr`
85
86			`wb_adr_i`
87			`72`
88
89
90
91
92
93			`wdata`
94
95			`wb_dat_i`
96			`310`
97
98
99
100
101
102			`rdata`
103
104			`wb_dat_o`
105			`310`
106
107
108
109
110
111			`sel`
112
113			`wb_sel_i`
114			`30`
115
116
117
118
119
120
121			`ack`
122
123			`wb_ack_o`
124
125
126
127
128
129			`cyc`
130
131			`wb_cyc_i`
132
133
134
135
136
137
138			`stb`
139
140			`wb_stb_i`
141
142
143
144
145
146			`we`
147
148			`wb_we_i`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169	133	jt_eaton
170
171
172
173
174
175	131	jt_eaton	`gen_registers`
176	133	jt_eaton	`102.1`
177	131	jt_eaton	`none`
178			`common`
179			`./tools/regtool/gen_registers`
180
181
182			`bus_intf`
183			`wb`
184
185
186			`dest_dir`
187			`../verilog`
188
189
190
191
192
193
194
195
196			`gen_verilog`
197			`104.0`
198			`none`
199			`common`
200			`./tools/verilog/gen_verilog`
201
202
203			`destination`
204	134	jt_eaton	`wb_uart16550_bus32_lit`
205	131	jt_eaton
206
207
208
209
210
211
212
213
214
215
216
217
218
219			`fs-common`
220
221
222
223			`../verilog/top.body`
224			`verilogSourcefragment`
225
226
227
228
229
230
231
232			`fs-sim`
233
234
235			`../verilog/copyright.v`
236			`verilogSourceinclude`
237
238
239
240
241	134	jt_eaton	`../verilog/common/wb_uart16550_bus32_lit`
242	131	jt_eaton	`verilogSourcemodule`
243
244
245
246
247
248			`../verilog/defines`
249			`verilogSourceinclude`
250
251
252
253			`wb`
254			`../verilog/wb_uart16550_bus32_lit_wb`
255			`verilogSourcemodule`
256
257
258
259
260			`raminfr`
261			`../verilog/raminfr`
262			`verilogSourcemodule`
263
264
265
266			`receiver`
267			`../verilog/receiver`
268			`verilogSourcemodule`
269
270
271
272			`regs`
273			`../verilog/regs`
274			`verilogSourcemodule`
275
276
277
278			`rfifo`
279			`../verilog/rfifo`
280			`verilogSourcemodule`
281
282
283
284			`sync_flops`
285			`../verilog/sync_flops`
286			`verilogSourcemodule`
287
288
289
290			`tfifo`
291			`../verilog/tfifo`
292			`verilogSourcemodule`
293
294
295
296			`transmitter`
297			`../verilog/transmitter`
298			`verilogSourcemodule`
299
300
301
302			`wb_fsm`
303			`../verilog/wb_fsm`
304			`verilogSourcemodule`
305
306
307
308
309
310
311
312
313			`fs-syn`
314
315
316			`../verilog/copyright.v`
317			`verilogSourceinclude`
318
319
320
321
322	134	jt_eaton	`../verilog/common/wb_uart16550_bus32_lit`
323	131	jt_eaton	`verilogSourcemodule`
324
325
326
327
328
329			`../verilog/defines`
330			`verilogSourceinclude`
331
332
333
334			`wb`
335			`../verilog/wb_uart16550_bus32_lit_wb`
336			`verilogSourcemodule`
337
338
339
340
341			`raminfr`
342			`../verilog/raminfr`
343			`verilogSourcemodule`
344
345
346
347			`receiver`
348			`../verilog/receiver`
349			`verilogSourcemodule`
350
351
352
353			`regs`
354			`../verilog/regs`
355			`verilogSourcemodule`
356
357
358
359			`rfifo`
360			`../verilog/rfifo`
361			`verilogSourcemodule`
362
363
364
365			`sync_flops`
366			`../verilog/sync_flops`
367			`verilogSourcemodule`
368
369
370
371			`tfifo`
372			`../verilog/tfifo`
373			`verilogSourcemodule`
374
375
376
377			`transmitter`
378			`../verilog/transmitter`
379			`verilogSourcemodule`
380
381
382
383			`wb_fsm`
384			`../verilog/wb_fsm`
385			`verilogSourcemodule`
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403			`verilog`
404
405
406			`spirit:library="Testbench"`
407			`spirit:name="toolflow"`
408			`spirit:version="verilog"/>`
409
410
411
412
413
414
415
416
417			`commoncommon`
418
419			`Verilog`
420
421
422			`fs-common`
423
424
425
426
427
428			`sim:Simulation:`
429
430			`Verilog`
431
432
433			`fs-sim`
434
435
436
437
438			`syn:Synthesis:`
439
440			`Verilog`
441
442
443			`fs-syn`
444
445
446
447
448
449
450			`doc`
451
452
453			`spirit:library="Testbench"`
454			`spirit:name="toolflow"`
455			`spirit:version="documentation"/>`
456
457			`:Documentation:`
458			`Verilog`
459
460
461
462
463
464
465
466
467
468
469
470			`baud_o`
471			`wire`
472			`out`
473
474
475			`cts_pad_i`
476			`wire`
477			`in`
478
479
480			`dcd_pad_i`
481			`wire`
482			`in`
483
484
485			`dsr_pad_i`
486			`wire`
487			`in`
488
489
490			`dtr_pad_o`
491			`wire`
492			`out`
493
494
495			`int_o`
496			`wire`
497			`out`
498
499
500
501			`ri_pad_i`
502			`wire`
503			`in`
504
505
506			`rts_pad_o`
507			`wire`
508			`out`
509
510
511			`srx_pad_i`
512			`wire`
513			`in`
514
515
516			`stx_pad_o`
517			`wire`
518			`out`
519
520
521
522
523
524
525
526
527
528
529
530
531
532			`wb`
533			`8`
534
535			`wb`
536			`0x00`
537
538
539			`mb_microbus`
540			`0x100`
541			`32`
542
543
544
545			`rb_dll_reg`
546			`0x0`
547			`8`
548			`read-only`
549
550
551
552			`tr_reg`
553			`0x0`
554			`8`
555			`write-strobe`
556
557
558
559
560			`ie_dlh_reg`
561			`0x1`
562			`8`
563			`read-only`
564
565
566
567			`ie_reg`
568			`0x1`
569			`4`
570			`write-strobe`
571
572
573
574
575			`dll_reg`
576			`0x0`
577			`8`
578			`write-strobe`
579
580
581
582
583			`dlh_reg`
584			`0x1`
585			`8`
586			`write-strobe`
587
588
589
590
591
592
593			`ii_reg`
594			`0x2`
595			`4`
596			`read-only`
597
598
599
600			`fc_reg`
601			`0x2`
602			`8`
603			`write-only`
604
605
606
607
608			`lc_reg`
609			`0x3`
610			`8`
611			`read-write`
612
613
614
615			`mc_reg`
616			`0x4`
617			`5`
618			`read-write`
619
620
621
622			`ls_reg`
623			`0x5`
624			`8`
625			`read-only`
626
627
628
629			`ms_reg`
630			`0x6`
631			`8`
632			`read-only`
633
634
635
636			`sr_reg`
637			`0x7`
638			`8`
639			`read-write`
640
641
642
643
644			`debug_0_reg`
645			`0x8`
646			`32`
647			`read-only`
648
649
650
651
652			`debug_1_reg`
653			`0xc`
654			`32`
655			`read-only`
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674