Subversion Repositories socgen

xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009

http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

opencores.org

wishbone

wb_uart16550

def  default

 wb_clk

        clk

        wb_clk_i

 wb_reset

        reset

        wb_rst_i

wb

   little

   8

         adr

         wb_adr_i

           wb_addr_width-10

         wdata

         wb_dat_i

           wb_data_width-10

         rdata

         wb_dat_o

           wb_data_width-10

         sel

         wb_sel_i

         ack

         wb_ack_o

         cyc

         wb_cyc_i

         stb

         wb_stb_i

         we

         wb_we_i

  elab_verilog

  102.1

  none

  :*Simulation:*

  ./tools/verilog/elab_verilog

      dest_dir

      io_ports

  gen_registers

  102.1

  none

  common

  ./tools/regtool/gen_registers

      bus_intf

      wb

      dest_dir

      ../verilog

  gen_verilog

  104.0

  none

  common

  ./tools/verilog/gen_verilog

      destination

      top

      dest_dir

      ../verilog

      fs-sim

        ../verilog/copyright.v

        verilogSourceinclude

        ../verilog/common/top

        verilogSourcemodule

        ../verilog/defines

        verilogSourceinclude

        wb

        ../verilog/wb_uart16550_def_wb

        verilogSourcemodule

        raminfr

        ../verilog/raminfr

        verilogSourcemodule

        receiver

        ../verilog/receiver

        verilogSourcemodule

        regs

        ../verilog/regs

        verilogSourcemodule

        rfifo

        ../verilog/rfifo

        verilogSourcemodule

        sync_flops

        ../verilog/sync_flops

        verilogSourcemodule

        tfifo

        ../verilog/tfifo

        verilogSourcemodule

        transmitter

        ../verilog/transmitter

        verilogSourcemodule

        wb_fsm

        ../verilog/wb_fsm

        verilogSourcemodule

      fs-syn

        ../verilog/copyright.v

        verilogSourceinclude

        ../verilog/common/top

        verilogSourcemodule

        ../verilog/defines

        verilogSourceinclude

        wb

        ../verilog/wb_uart16550_def_wb

        verilogSourcemodule

        raminfr

        ../verilog/raminfr

        verilogSourcemodule

        receiver

        ../verilog/receiver

        verilogSourcemodule

        regs

        ../verilog/regs

        verilogSourcemodule

        rfifo

        ../verilog/rfifo

        verilogSourcemodule

        sync_flops

        ../verilog/sync_flops

        verilogSourcemodule

        tfifo

        ../verilog/tfifo

        verilogSourcemodule

        transmitter

        ../verilog/transmitter

        verilogSourcemodule

        wb_fsm

        ../verilog/wb_fsm

        verilogSourcemodule

      fs-common

        ../verilog/top.body

        verilogSourcefragment

              verilog

                                   spirit:library="Testbench"

                                   spirit:name="toolflow"

                                   spirit:version="verilog"/>

              commoncommon

              Verilog

                            fs-common

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   spirit:library="Testbench"

                                   spirit:name="toolflow"

                                   spirit:version="documentation"/>

              :*Documentation:*

              Verilog

wb_addr_width8

wb_data_width8

wb_byte_lanes1

PRESCALER_PRESET16'h1234

baud_o

  wire

  out

cts_pad_i

  wire

  in

dcd_pad_i

  wire

  in

dsr_pad_i

  wire

  in

dtr_pad_o

  wire

  out

int_o

  wire

  out

ri_pad_i

  wire

  in

rts_pad_o

  wire

  out

srx_pad_i

  wire

  in

stx_pad_o

  wire

  out

8

 wb

 wb

 0x00

  mb_microbus

  0x100

  8

   rb_dll_reg

   0x0

   8

   read-only

   tr_reg

   0x0

   8

   write-strobe

   ie_dlh_reg

   0x1

   8

   read-only

   ie_reg

   0x1

   4

   write-strobe

   dll_reg

   0x0

   8

   write-strobe

   dlh_reg

   0x1

   8

   write-strobe

   ii_reg

   0x2

   4

   read-only

   fc_reg

   0x2

   8

   write-only

   lc_reg

   0x3

   8

   read-write

   bits

   Bits in character

   0

   2

   sb

   Stop bits

   2

   1

   pe

   Parity enable

   3

   1

   ep

   Even parity

   4

   1

   sp

   Stick parity

   5

   1

   bc

   Break control

   6

   1

   dlab

   Divsior latch access bit

   7

   1

   mc_reg

   0x4

   5

   read-write

   dtr

   Data transmit ready

   0

   1

   rts

   Ready to Send

   1

   1

   out

   Output control

   2

   2

   loopback

   loopback control

   4

   1

   ls_reg

   0x5

   8

   read-only

   ms_reg

   0x6

   8

   read-only

   sr_reg

   0x7

   8

   read-write

   debug_0_reg

   0x8

   32

   read-only

   debug_1_reg

   0xc

   32

   read-only