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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [icarus/] [default/] [test_define] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
`include  "../../testbenches/elab/wb_uart16550_def_tb/sw/wb.v"
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reg [31:0] d;
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initial
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 begin
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 $display("              ");
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 $display("          ===================================================");
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 $display("%t  Test Start",$realtime  );
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 $display("          ===================================================");
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 $display("              ");
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 test.cg.next(1);
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 test.cts_pad_R  <= 1'b0;
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 test.dcd_pad_R  <= 1'b0;
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 test.dsr_pad_R  <= 1'b0;
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 test.ri_pad_R   <= 1'b0;
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 test.cg.next(8);
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 $display("%t    out of reset  ",$realtime  );
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 test.cg.next(88);
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fork
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begin
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          test.i_wb_master.wb_write(fc_reg,1'b1,8'hc7 );
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          test.cg.next(20);
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          test.i_wb_master.wb_write(ie_reg,1'b1,8'h00 );
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          test.cg.next(20);
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          test.i_wb_master.wb_write(lc_reg,1'b1,8'h03 );
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          test.cg.next(20);
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          test.i_wb_master.wb_write(lc_reg,1'b1,8'h83 );
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          test.cg.next(20);
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          test.i_wb_master.wb_write(tr_reg,1'b1,8'h0d );
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          test.cg.next(20);
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          test.i_wb_master.wb_write(ie_reg,1'b1,8'h00 );
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          test.cg.next(20);
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          test.i_wb_master.wb_write(lc_reg,1'b1,8'h03 );
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          test.cg.next(20);
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          test.i_wb_master.wb_write(tr_reg,1'b1,8'h48 );
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          test.i_wb_master.wb_read(ls_reg,d );
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          test.cg.next(10000);
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          test.i_wb_master.wb_write(tr_reg,1'b1,8'h65 );
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          test.cg.next(10000);
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          test.i_wb_master.wb_write(tr_reg,1'b1,8'h6c );
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          test.cg.next(10000);
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          test.i_wb_master.wb_write(tr_reg,1'b1,8'h6c );
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          test.cg.next(10000);
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          test.i_wb_master.wb_write(tr_reg,1'b1,8'h6f );
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          test.cg.next(50000);
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          test.i_wb_master.wb_cmp(tr_reg,1'b1,8'h34 );
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          test.cg.next(50);
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          test.i_wb_master.wb_cmp(ie_reg,1'b1,8'h00 );
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          test.cg.next(50);
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          test.i_wb_master.wb_cmp(ii_reg,1'b1,8'hc1 );
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          test.cg.next(50);
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          test.i_wb_master.wb_cmp(lc_reg,1'b1,8'h03 );
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          test.cg.next(50);
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          test.i_wb_master.wb_cmp(mc_reg,1'b1,8'h00 );
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          test.cg.next(50);
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          test.i_wb_master.wb_cmp(ls_reg,1'b1,8'h61 );
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          test.cg.next(50);
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          test.i_wb_master.wb_cmp(ms_reg,1'b1,8'h00 );
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          test.cg.next(50);
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          test.i_wb_master.wb_cmp(sr_reg,1'b1,8'h00 );
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          test.cg.next(100);
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          test.i_wb_master.wb_cmp(tr_reg,1'b1,8'h43 );
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          test.cg.next(100);
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          test.i_wb_master.wb_cmp(tr_reg,1'b1,8'h56 );
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          test.cg.next(500);
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          test.i_wb_master.wb_cmp(debug_0_reg,1'b1,8'h60 );
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          test.cg.next(50);
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          test.i_wb_master.wb_cmp(debug_0_reg+1,1'b1,8'h10 );
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          test.cg.next(50);
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          test.i_wb_master.wb_cmp(debug_0_reg+2,1'b1,8'h03 );
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          test.cg.next(50);
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          test.i_wb_master.wb_cmp(debug_0_reg+3,1'b1,8'h00 );
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          test.cg.next(500);
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end
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 begin
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 test.uart_model.rx_parity_enable  = 1'b0;
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 test.uart_model.txd_parity_enable = 1'b0;
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 test.uart_model.rx_parity         = 1'b1;
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 test.uart_model.txd_parity        = 1'b1;
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 test.cg.next(10);
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 test.uart_model.rcv_byte(8'h48);
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 test.uart_model.send_byte(8'h34);
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 test.cg.next(10);
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 test.uart_model.rcv_byte(8'h65);
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 test.cg.next(10);
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 test.uart_model.rcv_byte(8'h6c);
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 test.cg.next(10);
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 test.uart_model.rcv_byte(8'h6c);
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 test.cg.next(10);
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 test.uart_model.rcv_byte(8'h6f);
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 test.cg.next(10);
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 test.uart_model.send_byte(8'h43);
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 test.cg.next(10);
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 test.uart_model.send_byte(8'h56);
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 end
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 join
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 test.cg.exit;
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end
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