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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_lit_lint.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus16_lit_lint
 
 
 
 
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 

  gen_design
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/gen_design
    
    
      dest_dir
      io_ports
    
  

 

 
 
 

 
 
       
 
 
              
              Dut
              
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bus16_lit_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
      
 
 
 
 
 
 

 
 
 
 
 
  
 
 
 
 
 
 
 
    
      fs-lint
 
 
 
      
        
        ../verilog/lint/wb_uart16550_bus16_lit_lint
        verilogSource
        module
      
 
 
 
 
 
    
 
 
 
 
  
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus16_lit_lint`
41
42
43
44
45
46	133	jt_eaton
47	131	jt_eaton
48	133	jt_eaton
49			`elab_verilog`
50			`102.1`
51			`none`
52			`:Simulation:`
53			`>`
54			`./tools/verilog/elab_verilog`
55
56
57			`configuration`
58			`default`
59
60
61			`dest_dir`
62			`io_ports`
63
64
65
66	131	jt_eaton
67	133	jt_eaton
68			`gen_design`
69			`102.1`
70			`none`
71			`:Simulation:`
72			`>`
73			`./tools/verilog/gen_design`
74
75
76			`dest_dir`
77			`io_ports`
78
79
80
81	131	jt_eaton
82	133	jt_eaton
83
84
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86	131	jt_eaton
87
88
89
90
91
92
93			`Dut`
94
95
96			`spirit:library="wishbone"`
97			`spirit:name="wb_uart16550"`
98			`spirit:version="bus16_lit_dut.params"/>`
99
100
101
102
103
104			`lint`
105			`:Lint:`
106			`Verilog`
107			`fs-lint`
108
109
110
111			`rtl_check`
112
113
114			`spirit:library="Testbench"`
115			`spirit:name="toolflow"`
116			`spirit:version="rtl_check"/>`
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
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142			`fs-lint`
143
144
145
146
147
148			`../verilog/lint/wb_uart16550_bus16_lit_lint`
149			`verilogSource`
150			`module`
151
152
153
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_lit_lint.xml] - Blame information for rev 133