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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_lit_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus16_lit_tb
 
 
 
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.bus16_lit_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
       
 
              
              Params
              
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bus16_lit_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              headersheaders
              Verilog
              
              
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
 
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 
 

 
 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
    
      fs-sim
 
 
 
      
        
        ../verilog/common/top.bus16_lit_tb
        verilogSourcemodule
      
 
 
 
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.bus16_lit_tb
        verilogSourcemodule
      
 
 
 
 
 
    
 
 
 
 
  
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_lit_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus16_lit_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59			`destination`
60			`top.bus16_lit_tb`
61
62
63			`dest_dir`
64			`../verilog`
65
66
67			`top`
68
69
70
71
72
73
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75
76
77
78
79
80			`UART_MODEL_CLKCNT4'b1100`
81			`UART_MODEL_SIZE4`
82
83
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85
86
87
88			`Params`
89
90
91			`spirit:library="wishbone"`
92			`spirit:name="wb_uart16550"`
93			`spirit:version="bus16_lit_dut.params"/>`
94
95
96
97
98
99			`Bfm`
100
101			`spirit:library="wishbone"`
102			`spirit:name="wb_uart16550"`
103			`spirit:version="bfm.design"/>`
104
105
106
107
108
109			`icarus`
110
111
112			`spirit:library="Testbench"`
113			`spirit:name="toolflow"`
114			`spirit:version="icarus"/>`
115
116
117
118
119
120
121
122			`headersheaders`
123			`Verilog`
124
125
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127
128			`commoncommon`
129			`Verilog`
130
131
132			`fs-common`
133
134
135
136
137
138
139			`sim:Simulation:`
140			`Verilog`
141
142
143			`fs-sim`
144
145
146
147
148			`lint:Lint:`
149			`Verilog`
150
151
152			`fs-lint`
153
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174			`fs-common`
175
176
177
178			`../verilog/tb.ext`
179			`verilogSourcefragment`
180
181
182
183
184
185
186
187
188
189			`fs-sim`
190
191
192
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194
195			`../verilog/common/top.bus16_lit_tb`
196			`verilogSourcemodule`
197
198
199
200
201
202
203
204
205
206
207
208			`fs-lint`
209
210
211
212			`../verilog/common/top.bus16_lit_tb`
213			`verilogSourcemodule`
214
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