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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_lit_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus16_lit_tb
 
 
 
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      wb_uart16550_bus16_lit_tb
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
       
 
              
              Params
              
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bus16_lit_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              headersheaders
              Verilog
              
              
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
 
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 
 

 
 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
    
      fs-sim
 
 
 
      
        
        ../verilog/common/wb_uart16550_bus16_lit_tb
        verilogSourcemodule
      
 
 
 
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/wb_uart16550_bus16_lit_tb
        verilogSourcemodule
      
 
 
 
 
 
    
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus16_lit_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59			`destination`
60	134	jt_eaton	`wb_uart16550_bus16_lit_tb`
61	131	jt_eaton
62
63
64
65
66
67
68
69
70
71
72
73			`UART_MODEL_CLKCNT4'b1100`
74			`UART_MODEL_SIZE4`
75
76
77
78
79
80
81			`Params`
82
83
84			`spirit:library="wishbone"`
85			`spirit:name="wb_uart16550"`
86			`spirit:version="bus16_lit_dut.params"/>`
87
88
89
90
91
92			`Bfm`
93
94			`spirit:library="wishbone"`
95			`spirit:name="wb_uart16550"`
96			`spirit:version="bfm.design"/>`
97
98
99
100
101
102			`icarus`
103
104
105			`spirit:library="Testbench"`
106			`spirit:name="toolflow"`
107			`spirit:version="icarus"/>`
108
109
110
111
112
113
114
115			`headersheaders`
116			`Verilog`
117
118
119
120
121			`commoncommon`
122			`Verilog`
123
124
125			`fs-common`
126
127
128
129
130
131
132			`sim:Simulation:`
133			`Verilog`
134
135
136			`fs-sim`
137
138
139
140
141			`lint:Lint:`
142			`Verilog`
143
144
145			`fs-lint`
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167			`fs-common`
168
169
170
171			`../verilog/tb.ext`
172			`verilogSourcefragment`
173
174
175
176
177
178
179
180
181
182			`fs-sim`
183
184
185
186
187
188	134	jt_eaton	`../verilog/common/wb_uart16550_bus16_lit_tb`
189	131	jt_eaton	`verilogSourcemodule`
190
191
192
193
194
195
196
197
198
199
200
201			`fs-lint`
202
203
204
205	134	jt_eaton	`../verilog/common/wb_uart16550_bus16_lit_tb`
206	131	jt_eaton	`verilogSourcemodule`
207
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_lit_tb.xml] - Blame information for rev 134