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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_lit_tb
 
 
 
 
 
 
 

 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      wb_uart16550_bus32_lit_tb
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
       
 
 
              
              Params
 
              
                
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_uart16550"
                                   ipxact:version="bus32_lit_dut.params"/>
 
 
 
 
             
              
 
 
              
              Bfm
 
              
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_uart16550"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              headersheaders
              Verilog
              
              
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/wb_uart16550_bus32_lit_tb
        verilogSourcemodule
      
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/wb_uart16550_bus32_lit_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_lit_tb`
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49	131	jt_eaton
50
51
52
53
54
55
56	135	jt_eaton
57			`gen_verilog`
58			`104.0`
59			`none`
60			`:common:`
61			`tools/verilog/gen_verilog`
62
63
64			`destination`
65			`wb_uart16550_bus32_lit_tb`
66
67
68
69	131	jt_eaton
70
71
72	135	jt_eaton
73	131	jt_eaton
74
75
76	135	jt_eaton
77
78			`UART_MODEL_CLKCNT4'b1100`
79			`UART_MODEL_SIZE4`
80
81	131	jt_eaton
82
83
84	135	jt_eaton
85	131	jt_eaton
86
87	135	jt_eaton
88			`Params`
89	131	jt_eaton
90	135	jt_eaton
91
92			`ipxact:library="wishbone"`
93			`ipxact:name="wb_uart16550"`
94			`ipxact:version="bus32_lit_dut.params"/>`
95	131	jt_eaton
96
97
98
99	135	jt_eaton
100
101	131	jt_eaton
102
103	135	jt_eaton
104			`Bfm`
105	131	jt_eaton
106	135	jt_eaton
107			`ipxact:library="wishbone"`
108			`ipxact:name="wb_uart16550"`
109			`ipxact:version="bfm.design"/>`
110
111	131	jt_eaton
112
113
114	135	jt_eaton
115			`headersheaders`
116			`Verilog`
117
118
119	131	jt_eaton
120	135	jt_eaton
121			`icarus`
122
123
124			`ipxact:library="Testbench"`
125			`ipxact:name="toolflow"`
126			`ipxact:version="icarus"/>`
127
128
129	131	jt_eaton
130
131	135	jt_eaton
132			`common:common:`
133			`Verilog`
134
135
136			`fs-common`
137
138
139	131	jt_eaton
140	135	jt_eaton
141			`sim:Simulation:`
142			`Verilog`
143
144
145			`fs-sim`
146
147
148	131	jt_eaton
149	135	jt_eaton
150			`lint:Lint:`
151			`Verilog`
152
153
154			`fs-lint`
155
156
157	131	jt_eaton
158
159	135	jt_eaton
160	131	jt_eaton
161
162
163
164
165
166	135	jt_eaton
167	131	jt_eaton
168
169
170	135	jt_eaton
171	131	jt_eaton
172
173
174	135	jt_eaton
175			`fs-common`
176	131	jt_eaton
177	135	jt_eaton
178
179			`../verilog/tb.ext`
180			`verilogSourcefragment`
181
182	131	jt_eaton
183	135	jt_eaton
184	131	jt_eaton
185
186
187
188
189
190	135	jt_eaton
191			`fs-sim`
192	131	jt_eaton
193	135	jt_eaton
194
195			`../verilog/common/wb_uart16550_bus32_lit_tb`
196			`verilogSourcemodule`
197
198	131	jt_eaton
199
200	135	jt_eaton
201	131	jt_eaton
202
203	135	jt_eaton
204			`fs-lint`
205	131	jt_eaton
206	135	jt_eaton
207
208			`../verilog/common/wb_uart16550_bus32_lit_tb`
209			`verilogSourcemodule`
210
211	131	jt_eaton
212
213
214	135	jt_eaton
215	131	jt_eaton
216
217
218
219
220
221	135	jt_eaton
222	131	jt_eaton
223
224
225
226	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_tb.xml] - Blame information for rev 135