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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_lit_tb
 
 
 
 
 
 
 

 
 
 
 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog

 

  trace_bus
  103.0
  none
  :*Simulation:*
  ./tools/verilog/trace_bus
    
    
      path
      root.dut
    
    
      bus_name
      wb
    
  

 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.bus32_lit_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
       
 
 
              
              Params
 
              
                
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bus32_lit_dut.params"/>
 
 
 
 
             
              
 
 
              
              Bfm
 
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              headersheaders
              Verilog
              
              
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.bus32_lit_tb
        verilogSourcemodule
      
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.bus32_lit_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_tb.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_lit_tb`
41
42
43
44
45
46
47
48
49
50
51
52
53
54			`elab_verilog`
55			`103.0`
56			`none`
57			`:Simulation:`
58			`./tools/verilog/elab_verilog`
59
60
61
62			`trace_bus`
63			`103.0`
64			`none`
65			`:Simulation:`
66			`./tools/verilog/trace_bus`
67
68
69			`path`
70			`root.dut`
71
72
73			`bus_name`
74			`wb`
75
76
77
78
79
80
81
82
83
84
85			`gen_verilog`
86			`104.0`
87			`none`
88			`common`
89			`./tools/verilog/gen_verilog`
90
91
92			`destination`
93			`top.bus32_lit_tb`
94
95
96			`dest_dir`
97			`../verilog`
98
99
100			`top`
101
102
103
104
105
106
107
108
109
110
111
112
113			`UART_MODEL_CLKCNT4'b1100`
114			`UART_MODEL_SIZE4`
115
116
117
118
119
120
121
122
123			`Params`
124
125
126
127			`spirit:library="wishbone"`
128			`spirit:name="wb_uart16550"`
129			`spirit:version="bus32_lit_dut.params"/>`
130
131
132
133
134
135
136
137
138
139			`Bfm`
140
141
142			`spirit:library="wishbone"`
143			`spirit:name="wb_uart16550"`
144			`spirit:version="bfm.design"/>`
145
146
147
148
149
150			`headersheaders`
151			`Verilog`
152
153
154
155
156			`icarus`
157
158
159			`spirit:library="Testbench"`
160			`spirit:name="toolflow"`
161			`spirit:version="icarus"/>`
162
163
164
165
166
167			`commoncommon`
168			`Verilog`
169
170
171			`fs-common`
172
173
174
175
176			`sim:Simulation:`
177			`Verilog`
178
179
180			`fs-sim`
181
182
183
184
185			`lint:Lint:`
186			`Verilog`
187
188
189			`fs-lint`
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210			`fs-common`
211
212
213
214			`../verilog/tb.ext`
215			`verilogSourcefragment`
216
217
218
219
220
221
222
223
224
225
226			`fs-sim`
227
228
229
230			`../verilog/common/top.bus32_lit_tb`
231			`verilogSourcemodule`
232
233
234
235
236
237
238
239			`fs-lint`
240
241
242
243			`../verilog/common/top.bus32_lit_tb`
244			`verilogSourcemodule`
245
246
247
248
249
250
251
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