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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_lit_tb
 
 
 
 
 
 
 

 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.bus32_lit_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
       
 
 
              
              Params
 
              
                
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bus32_lit_dut.params"/>
 
 
 
 
             
              
 
 
              
              Bfm
 
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              headersheaders
              Verilog
              
              
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.bus32_lit_tb
        verilogSourcemodule
      
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.bus32_lit_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_lit_tb`
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57			`gen_verilog`
58			`104.0`
59			`none`
60			`common`
61			`./tools/verilog/gen_verilog`
62
63
64			`destination`
65			`top.bus32_lit_tb`
66
67
68			`dest_dir`
69			`../verilog`
70
71
72			`top`
73
74
75
76
77
78
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81
82
83
84
85			`UART_MODEL_CLKCNT4'b1100`
86			`UART_MODEL_SIZE4`
87
88
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93
94
95			`Params`
96
97
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99			`spirit:library="wishbone"`
100			`spirit:name="wb_uart16550"`
101			`spirit:version="bus32_lit_dut.params"/>`
102
103
104
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109
110
111			`Bfm`
112
113
114			`spirit:library="wishbone"`
115			`spirit:name="wb_uart16550"`
116			`spirit:version="bfm.design"/>`
117
118
119
120
121
122			`headersheaders`
123			`Verilog`
124
125
126
127
128			`icarus`
129
130
131			`spirit:library="Testbench"`
132			`spirit:name="toolflow"`
133			`spirit:version="icarus"/>`
134
135
136
137
138
139			`commoncommon`
140			`Verilog`
141
142
143			`fs-common`
144
145
146
147
148			`sim:Simulation:`
149			`Verilog`
150
151
152			`fs-sim`
153
154
155
156
157			`lint:Lint:`
158			`Verilog`
159
160
161			`fs-lint`
162
163
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170
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172
173
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176
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180
181
182			`fs-common`
183
184
185
186			`../verilog/tb.ext`
187			`verilogSourcefragment`
188
189
190
191
192
193
194
195
196
197
198			`fs-sim`
199
200
201
202			`../verilog/common/top.bus32_lit_tb`
203			`verilogSourcemodule`
204
205
206
207
208
209
210
211			`fs-lint`
212
213
214
215			`../verilog/common/top.bus32_lit_tb`
216			`verilogSourcemodule`
217
218
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