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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_lit_tb
 
 
 
 
 
 
 

 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      wb_uart16550_bus32_lit_tb
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
       
 
 
              
              Params
 
              
                
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bus32_lit_dut.params"/>
 
 
 
 
             
              
 
 
              
              Bfm
 
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              headersheaders
              Verilog
              
              
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/wb_uart16550_bus32_lit_tb
        verilogSourcemodule
      
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/wb_uart16550_bus32_lit_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_lit_tb`
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57			`gen_verilog`
58			`104.0`
59			`none`
60			`common`
61			`./tools/verilog/gen_verilog`
62
63
64			`destination`
65	134	jt_eaton	`wb_uart16550_bus32_lit_tb`
66	131	jt_eaton
67
68
69
70
71
72
73
74
75
76
77
78			`UART_MODEL_CLKCNT4'b1100`
79			`UART_MODEL_SIZE4`
80
81
82
83
84
85
86
87
88			`Params`
89
90
91
92			`spirit:library="wishbone"`
93			`spirit:name="wb_uart16550"`
94			`spirit:version="bus32_lit_dut.params"/>`
95
96
97
98
99
100
101
102
103
104			`Bfm`
105
106
107			`spirit:library="wishbone"`
108			`spirit:name="wb_uart16550"`
109			`spirit:version="bfm.design"/>`
110
111
112
113
114
115			`headersheaders`
116			`Verilog`
117
118
119
120
121			`icarus`
122
123
124			`spirit:library="Testbench"`
125			`spirit:name="toolflow"`
126			`spirit:version="icarus"/>`
127
128
129
130
131
132			`commoncommon`
133			`Verilog`
134
135
136			`fs-common`
137
138
139
140
141			`sim:Simulation:`
142			`Verilog`
143
144
145			`fs-sim`
146
147
148
149
150			`lint:Lint:`
151			`Verilog`
152
153
154			`fs-lint`
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175			`fs-common`
176
177
178
179			`../verilog/tb.ext`
180			`verilogSourcefragment`
181
182
183
184
185
186
187
188
189
190
191			`fs-sim`
192
193
194
195	134	jt_eaton	`../verilog/common/wb_uart16550_bus32_lit_tb`
196	131	jt_eaton	`verilogSourcemodule`
197
198
199
200
201
202
203
204			`fs-lint`
205
206
207
208	134	jt_eaton	`../verilog/common/wb_uart16550_bus32_lit_tb`
209	131	jt_eaton	`verilogSourcemodule`
210
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_tb.xml] - Blame information for rev 134