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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_def_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
def_tb
 
 
 
 
 
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 
 
 
 

 
 

 
 

    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
 
 
       
 
 
              
              Params
              
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="def_dut.params"/>
              
              
 
 
              
              Bfm
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              headersheaders
              Verilog
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
 
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_def_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog`
52			`104.0`
53			`none`
54			`common`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59			`top.tb`
60
61
62			`dest_dir`
63			`../verilog`
64
65
66			`top`
67
68
69
70
71
72
73
74
75
76
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81
82
83			`UART_MODEL_CLKCNT4'b1100`
84			`UART_MODEL_SIZE4`
85
86
87
88
89
90
91
92
93
94
95			`Params`
96
97
98			`spirit:library="wishbone"`
99			`spirit:name="wb_uart16550"`
100			`spirit:version="def_dut.params"/>`
101
102
103
104
105
106			`Bfm`
107
108			`spirit:library="wishbone"`
109			`spirit:name="wb_uart16550"`
110			`spirit:version="bfm.design"/>`
111
112
113
114
115			`icarus`
116
117
118			`spirit:library="Testbench"`
119			`spirit:name="toolflow"`
120			`spirit:version="icarus"/>`
121
122
123
124
125
126
127
128			`headersheaders`
129			`Verilog`
130
131
132
133
134
135
136			`commoncommon`
137			`Verilog`
138
139
140			`fs-common`
141
142
143
144
145
146
147			`sim:Simulation:`
148			`Verilog`
149
150
151			`fs-sim`
152
153
154
155
156			`lint:Lint:`
157			`Verilog`
158
159
160			`fs-lint`
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
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178
179
180			`fs-common`
181
182
183
184			`../verilog/tb.ext`
185			`verilogSourcefragment`
186
187
188
189
190
191
192
193
194
195			`fs-sim`
196
197
198
199			`../verilog/common/top.tb`
200			`verilogSourcemodule`
201
202
203
204
205
206
207
208
209			`fs-lint`
210
211
212
213			`../verilog/common/top.tb`
214			`verilogSourcemodule`
215
216
217
218
219
220
221
222
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228