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jt_eaton |
T6502 Embedded Microprocessor
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==================================================================================
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The T6502 IP is a processor that uses most of MosTechnology M6502 processor instructions
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and processor registers.It has been updated for a synthesized embedded design in a FGPA or ASIC.
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It differs from the original Mos6502 in the following ways
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1) Changed memory interface from asynchronous to synchronous.
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2) Number of clock cycles to execute instructions has changed
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3) Page Zero is fully filled with SRAM. Page zero is not usable as I/O space
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An extended version is also avaiable. Before we can extend we must first remove some features that either
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did not make sense at the time or made only made sense for a 40 pin part sitting in a sea or ttl parts.
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1) Remove Binary Coded Decimal mode. The D bit in the PSR does nothing.
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2) Moved stack from Page 01 into a seperate RAM. Stack size is now parameterized and only accessable via
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pushes and pulls.Removed the TSX and TXS commands. If you need to manipulate the stack pointer and stack
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data then you really should get a more powerfull processor
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3) Replaced old interrupt/brk system with vectored interrupt. Masking is done externally and vectors provide
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as many interrupts as you like. PSR is not pushed on interrupt and rts/rti become one instruction
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4) Indirect addresses stored in page 00 MUST be aligned on even addresses. This is done by shifting a
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page zero indirect address bu one bit and using both page 00 and 01.
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5) Bit (5) of the PSR is now a run bit. Forcing it to 0 will halt the processor until the next reset/interrupt
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6) Added Debugging logic and error checking
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7) self modifying code is no longer supported. You must provide a single rom image with all executable code
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History
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=========================================================================================
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This component is derived from the opencores t6507lp project.
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The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini
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was a atari 2600 on a chip. This takes the t6507 portion and turns it into a fully functional updated 6502.
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Processor Model
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===============================================================================================
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+----------+
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| Acc | Accumulator (A)
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+----------+
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| X | X Index Register (X)
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+----------+
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| Y | Y Index Register (Y)
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+----------+----------+
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| PCH | PCL | Program Counter (PC)
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+----------+----------+
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| 00000001 | SP | Stack Pointer (SP)
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+----------+----------+
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| P | Processor Status Word (P)
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+----------+
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NV1BDIZC
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|||||||+---- Carry Flag 1 = True
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||||||+----- Zero Flag 1 = Result == 8'h00
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|||||+------ IRQ Disable 1 = Disable
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||||+------- Decimal Mode Not used
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|||+-------- Break Command 1 = In break routine
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||+--------- Run Mode 1 = Processor is running
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|+---------- Overflow Flag 1 = True
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+----------- Negative 1 = Negative Number
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Memory Model
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===============================================================================================
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0000-00FF | Page Zero RAM
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0010-01FF | Stack RAM
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0200-FFF9 | Program and Data RAM
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FFFA | NMI Vector Low
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FFFB | NMI Vector High
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FFFC | Boot Vector Low
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FFFD | Boot Vector High
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FFFE | IRQ/BRK Vector Low
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FFFF | IRQ/BRK Vector High
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Definitions
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===============================================================================================
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Opcode Current Instruction byte
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New_opcode Next Instruction byte
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Opc_Add Address of current instruction
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Next_Op_Add Address of next instruction byte
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Operand Data operand
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Address Address of data operand if in memory
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Offset Value added to Opc_Add if branch is taken
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Pointer Address to store the address of data opeand if in memory
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Vector Address to store the Next_Op_Add
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Instruction Set
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===============================================================================================
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Inst Description Effect on flags
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-----------------------------------------------------------------------------------------------
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ADC Operand Add Acc to Operand with Carry NZCV
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SBC Operand Subract Operand from Acc with Borrow NZXV
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AND Operand Logical AND Acc and Operand NZ
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CMP Operand Compare Acc with Operand NZC
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CPX Operand Compare X_index with Operand NZC
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CPY Operand Compare Y_index with Operand NZC
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EOR Operand Exclusive Or Acc with Operand NZ
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LDA Operand Load Operand into Acc NZ
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LDX Operand Load Operand into X_index NZ
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LDY Operand Load Operand into Y_index NZ
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ORA Operand Logical Or Acc with Operand NZ
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BIT Operand Bit Test Acc with operand Z67
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STA Address Store Acc @ address NONE
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STX Address Store X_Index @ address NONE
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STY Address Store Y_Index @ address NONE
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ASL Operand Arithmetic Shift Left Operand into Carry NZC
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DEC Operand Decrement Operand NZ
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INC Operand Incremement Operand NZ
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DEX Decrement X Index NZ
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INX Incremement X Index NZ
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DEY Decrement Y Index NZ
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INY Incremement Y Index NZ
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LSR Operand Logical Shift Right Operand into Carry NZC
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ROL Operand Rotate Left Operand thru Carry NZC
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ROR Operand Rotate Right Operand thru Carry NZC
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NOP No Operation NONE
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SEC Set Carry Flag 1 -> C
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SED Set Decimal Flag 1 -> D
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SEI Set Interrupt Flag 1 -> I
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CLC Clear Carry Flag 0 -> C
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CLD Clear Decimal Flag 0 -> D
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CLI Clear Interrupt Flag 0 -> I
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CLV Clear Overflow Flag 0 -> V
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TAX Transfer Acc into X_Index NZ
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TAY Transfer Acc into Y_Index NZ
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TXA Transfer X_Index into Acc NZ
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TYA Transfer Y_Index into Acc NZ
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BCC Offset Branch if C == 0 NONE
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BCS Offset Branch if C == 1 NONE
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BNE Offset Branch if Z == 0 NONE
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BEQ Offset Branch if Z == 1 NONE
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BVC Offset Branch if V == 0 NONE
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BVS Offset Branch if V == 1 NONE
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BPL Offset Branch if N == 0 NONE
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BMI Offset Branch if N == 1 NONE
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PLA Pull Acc from Stack NZ
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PLP Pull PSR from Stack RESTORE
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PHA Push Acc onto Stack NONE
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PHP Push PSR onto Stack NONE
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JMP Next_Op_Add Jump to New Address NONE
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JMP Vector Jump to New Address found by vector NONE
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JSR Next_Op_Add Save PC+2 on stack and jump to New Address NONE
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BRK Save status and PC+1 on stack and jump to New Address set 1 -> B
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RTI Pull Status and PC from stack RESTORED
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RTS Pull PC from stack NONE
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Definitions
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===============================================================================================
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Opcode Current Instruction byte
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New_opcode Next Instruction byte
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Opc_Add Address of current instruction
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Next_Op_Add Address of next instruction byte
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Operand Data operand
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Address Address of data operand if in memory
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Offset Value added to Opc_Add if branch is taken
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Pointer Address to store the address of data opeand if in memory
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Vector Address to store the Next_Op_Add
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Addressing Modes
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===============================================================================================
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Immediate Read
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-----------------------------------------------------------------------------------------------------
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Operand is located in memory following the opcode
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Opcode Operand
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Absolute Read/Write/ReadModifyWrite
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-----------------------------------------------------------------------------------------------------
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16 bit address of operand is located in memory following opcode (low byte,high byte)
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Opcode Address_l,Address_h
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Absolute Indexed Read/Write/ReadModifyWrite
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-----------------------------------------------------------------------------------------------------
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Operand is found by adding index value to 16 bit address following opcode.(no wraparound)
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Opcode Address_l,Address_h
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Page Zero Read/Write/ReadModifyWrite
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-----------------------------------------------------------------------------------------------------
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8 bit page zero address of operand is located in memory following opcode.
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Opcode Address_l
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Page Zero Indexed Read/Write/ReadModifyWrite
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-----------------------------------------------------------------------------------------------------
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Operand is found in page zero by adding index value to 8 bit address following opcode.(wraps around)
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Opcode Address_l
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Page Zero Indirect X Read/Write
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-----------------------------------------------------------------------------------------------------
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Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode and
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the upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)
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Opcode Pointer_l
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Page Zero Indirect Y Read/Write
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-----------------------------------------------------------------------------------------------------
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8 bit page zero address containing a 16 bit address is located in memory following opcode. Y index is added to this address
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(no wraparound).
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Opcode Pointer_l
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Implied Read/Write/Read_Modify_Write
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-----------------------------------------------------------------------------------------------------
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Operand is specified in the Opcode
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Opcode
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Branch Read
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-----------------------------------------------------------------------------------------------------
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Opcode is followed by the relative offset for the branch
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Opcode Offset
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Stack StackRead/StackWrite
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-----------------------------------------------------------------------------------------------------
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Operation uses the Stack
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Opcode
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Stack_Pointer
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-----------------------------------------------------------------------------------------------------
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Transfer between Stack_pointer and X index
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Opcode
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Jump Absolute Read
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-----------------------------------------------------------------------------------------------------
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16 bit destination address follows opcode
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Opcode Next_Op_add_l,Next_Op_add_h
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Jump Indirect Read
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-----------------------------------------------------------------------------------------------------
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16 bit Address following opcode points to destination address
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Opcode Vector_l, Vector_h
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JumpSub Absolute Read_Stackwrite
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-----------------------------------------------------------------------------------------------------
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16 bit destination address follows opcode. Return address is pushed on stack
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Opcode Next_Op_add_l,Next_Op_add_h
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Break Read_Stackwrite
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-----------------------------------------------------------------------------------------------------
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Return address is pushed on stack and the IRQ vector is taken
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Opcode
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| 417 |
|
|
Return from Interrupt Read_Stackread
|
| 418 |
|
|
-----------------------------------------------------------------------------------------------------
|
| 419 |
|
|
PSR and Prog_counter are pulled from stack
|
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
Opcode
|
| 423 |
|
|
|
| 424 |
|
|
|
| 425 |
|
|
|
| 426 |
|
|
|
| 427 |
|
|
|
| 428 |
|
|
Return from Subroutine Read_Stackread
|
| 429 |
|
|
-----------------------------------------------------------------------------------------------------
|
| 430 |
|
|
Prog_counter is pulled from stack
|
| 431 |
|
|
|
| 432 |
|
|
|
| 433 |
|
|
Opcode
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
|
| 437 |
|
|
|
| 438 |
|
|
|
| 439 |
|
|
|
| 440 |
|
|
|
| 441 |
|
|
|
| 442 |
|
|
|
| 443 |
|
|
|
| 444 |
|
|
|
| 445 |
|
|
|
| 446 |
|
|
|
| 447 |
|
|
|
| 448 |
|
|
|
| 449 |
|
|
|
| 450 |
|
|
|
| 451 |
|
|
|
| 452 |
|
|
|
| 453 |
|
|
|
| 454 |
|
|
|
| 455 |
|
|
|
| 456 |
|
|
|
| 457 |
|
|
Instruction Opcodes (hex)
|
| 458 |
|
|
====================================================================================================
|
| 459 |
|
|
|
| 460 |
|
|
|
| 461 |
|
|
|
| 462 |
|
|
ADC abs 6D
|
| 463 |
|
|
ADC abs,X 7D
|
| 464 |
|
|
ADC abs,Y 79
|
| 465 |
|
|
ADC #n 69
|
| 466 |
|
|
ADC zp 65
|
| 467 |
|
|
ADC (zp,X) 61
|
| 468 |
|
|
ADC zp,X 75
|
| 469 |
|
|
ADC (zp),Y 71
|
| 470 |
|
|
|
| 471 |
|
|
AND abs 2D
|
| 472 |
|
|
AND abs,X 3D
|
| 473 |
|
|
AND abs,Y 39
|
| 474 |
|
|
AND #n 29
|
| 475 |
|
|
AND zp 25
|
| 476 |
|
|
AND (zp,X) 21
|
| 477 |
|
|
AND zp,X 35
|
| 478 |
|
|
AND (zp),Y 31
|
| 479 |
|
|
|
| 480 |
|
|
ASL A 0A
|
| 481 |
|
|
ASL abs 0E
|
| 482 |
|
|
ASL abs,X 1E
|
| 483 |
|
|
ASL zp 06
|
| 484 |
|
|
ASL zp,X 16
|
| 485 |
|
|
|
| 486 |
|
|
BCC rel 90
|
| 487 |
|
|
BCS rel B0
|
| 488 |
|
|
BEQ rel F0
|
| 489 |
|
|
|
| 490 |
|
|
BIT abs 2C
|
| 491 |
|
|
BIT zp 24
|
| 492 |
|
|
|
| 493 |
|
|
BMI rel 30
|
| 494 |
|
|
BNE rel D0
|
| 495 |
|
|
BPL rel 10
|
| 496 |
|
|
|
| 497 |
|
|
BRK 00
|
| 498 |
|
|
|
| 499 |
|
|
BVC rel 50
|
| 500 |
|
|
BVS rel 70
|
| 501 |
|
|
|
| 502 |
|
|
|
| 503 |
|
|
CLC 18
|
| 504 |
|
|
CLD D8
|
| 505 |
|
|
CLI 58
|
| 506 |
|
|
CLV B8
|
| 507 |
|
|
|
| 508 |
|
|
CMP abs CD
|
| 509 |
|
|
CMP abs,X DD
|
| 510 |
|
|
CMP abs,Y D9
|
| 511 |
|
|
CMP #n C9
|
| 512 |
|
|
CMP zp C5
|
| 513 |
|
|
CMP (zp,X) C1
|
| 514 |
|
|
CMP zp,X D5
|
| 515 |
|
|
CMP (zp),Y D1
|
| 516 |
|
|
|
| 517 |
|
|
CPX abs EC
|
| 518 |
|
|
CPX #n E0
|
| 519 |
|
|
CPX zp E4
|
| 520 |
|
|
CPY abs CC
|
| 521 |
|
|
CPY #n C0
|
| 522 |
|
|
CPY zp C4
|
| 523 |
|
|
|
| 524 |
|
|
DEC abs CE
|
| 525 |
|
|
DEC abs,X DE
|
| 526 |
|
|
DEC zp C6
|
| 527 |
|
|
DEC zp,X D6
|
| 528 |
|
|
|
| 529 |
|
|
DEX CA
|
| 530 |
|
|
DEY 88
|
| 531 |
|
|
|
| 532 |
|
|
EOR abs 4D
|
| 533 |
|
|
EOR abs,X 5D
|
| 534 |
|
|
EOR abs,Y 59
|
| 535 |
|
|
EOR #n 49
|
| 536 |
|
|
EOR zp 45
|
| 537 |
|
|
EOR (zp,X) 41
|
| 538 |
|
|
EOR zp,X 55
|
| 539 |
|
|
EOR (zp),Y 51
|
| 540 |
|
|
|
| 541 |
|
|
INC abs EE
|
| 542 |
|
|
INC abs,X FE
|
| 543 |
|
|
INC zp E6
|
| 544 |
|
|
INC zp,X F6
|
| 545 |
|
|
INX E8
|
| 546 |
|
|
INY C8
|
| 547 |
|
|
|
| 548 |
|
|
JMP abs 4C
|
| 549 |
|
|
JMP (abs) 6C
|
| 550 |
|
|
JSR abs 20
|
| 551 |
|
|
|
| 552 |
|
|
LDA abs AD
|
| 553 |
|
|
LDA abs,X BD
|
| 554 |
|
|
LDA abs,Y B9
|
| 555 |
|
|
LDA #n A9
|
| 556 |
|
|
LDA zp A5
|
| 557 |
|
|
LDA (zp,X) A1
|
| 558 |
|
|
LDA zp,X B5
|
| 559 |
|
|
LDA (zp),Y B1
|
| 560 |
|
|
|
| 561 |
|
|
LDX abs AE
|
| 562 |
|
|
LDX abs,Y BE
|
| 563 |
|
|
LDX #n A2
|
| 564 |
|
|
LDX zp A6
|
| 565 |
|
|
LDX zp,Y B6
|
| 566 |
|
|
|
| 567 |
|
|
LDY abs AC
|
| 568 |
|
|
LDY abs,X BC
|
| 569 |
|
|
LDY #n A0
|
| 570 |
|
|
LDY zp A4
|
| 571 |
|
|
LDY zp,X B4
|
| 572 |
|
|
|
| 573 |
|
|
LSR A 4A
|
| 574 |
|
|
LSR abs 4E
|
| 575 |
|
|
LSR abs,X 5E
|
| 576 |
|
|
LSR zp 46
|
| 577 |
|
|
LSR zp,X 56
|
| 578 |
|
|
|
| 579 |
|
|
NOP EA
|
| 580 |
|
|
|
| 581 |
|
|
ORA abs 0D
|
| 582 |
|
|
ORA abs,X 1D
|
| 583 |
|
|
ORA abs,Y 19
|
| 584 |
|
|
ORA #n 09
|
| 585 |
|
|
ORA zp 05
|
| 586 |
|
|
ORA (zp,X) 01
|
| 587 |
|
|
ORA zp,X 15
|
| 588 |
|
|
ORA (zp),Y 11
|
| 589 |
|
|
|
| 590 |
|
|
PHA 48
|
| 591 |
|
|
PHP 08
|
| 592 |
|
|
|
| 593 |
|
|
PLA 68
|
| 594 |
|
|
PLP 28
|
| 595 |
|
|
|
| 596 |
|
|
ROL A 2A
|
| 597 |
|
|
ROL abs 2E
|
| 598 |
|
|
ROL abs,X 3E
|
| 599 |
|
|
ROL zp 26
|
| 600 |
|
|
ROL zp,X 36
|
| 601 |
|
|
|
| 602 |
|
|
ROR A 6A
|
| 603 |
|
|
ROR abs 6E
|
| 604 |
|
|
ROR abs,X 7E
|
| 605 |
|
|
ROR zp 66
|
| 606 |
|
|
ROR zp,X 76
|
| 607 |
|
|
|
| 608 |
|
|
RTI 40
|
| 609 |
|
|
|
| 610 |
|
|
RTS 60
|
| 611 |
|
|
|
| 612 |
|
|
SBC abs ED
|
| 613 |
|
|
SBC abs,X FD
|
| 614 |
|
|
SBC abs,Y F9
|
| 615 |
|
|
SBC #n E9
|
| 616 |
|
|
SBC zp E5
|
| 617 |
|
|
SBC (zp,X) E1
|
| 618 |
|
|
SBC zp,X F5
|
| 619 |
|
|
SBC (zp),Y F1
|
| 620 |
|
|
|
| 621 |
|
|
SEC 38
|
| 622 |
|
|
SED F8
|
| 623 |
|
|
SEI 78
|
| 624 |
|
|
|
| 625 |
|
|
STA abs 8D
|
| 626 |
|
|
STA abs,X 9D
|
| 627 |
|
|
STA abs,Y 99
|
| 628 |
|
|
STA zp 85
|
| 629 |
|
|
STA (zp,X) 81
|
| 630 |
|
|
STA zp,X 95
|
| 631 |
|
|
STA (zp),Y 91
|
| 632 |
|
|
|
| 633 |
|
|
STX abs 8E
|
| 634 |
|
|
STX zp 86
|
| 635 |
|
|
STX zpy 96
|
| 636 |
|
|
|
| 637 |
|
|
STY abs 8C
|
| 638 |
|
|
STY zp 84
|
| 639 |
|
|
STY zp,X 94
|
| 640 |
|
|
|
| 641 |
|
|
TAX AA
|
| 642 |
|
|
TAY A8
|
| 643 |
|
|
TXA 8A
|
| 644 |
|
|
TYA 98
|
| 645 |
|
|
|
| 646 |
|
|
|
| 647 |
|
|
|
| 648 |
|
|
|
| 649 |
|
|
|
| 650 |
|
|
|
| 651 |
|
|
|
| 652 |
|
|
|
| 653 |
|
|
|
| 654 |
|
|
Instruction Decode
|
| 655 |
|
|
======================================================================================================================================================
|
| 656 |
|
|
|
| 657 |
|
|
|
| 658 |
|
|
|
| 659 |
|
|
|
| 660 |
|
|
|
| 661 |
|
|
|
| 662 |
|
|
|
| 663 |
|
|
|
| 664 |
|
|
|
| 665 |
|
|
|
| 666 |
|
|
// alu_mode
|
| 667 |
|
|
`define alu_mode_add 3'b000
|
| 668 |
|
|
`define alu_mode_and 3'b001
|
| 669 |
|
|
`define alu_mode_orr 3'b010
|
| 670 |
|
|
`define alu_mode_eor 3'b011
|
| 671 |
|
|
`define alu_mode_sfl 3'b100
|
| 672 |
|
|
`define alu_mode_sfr 3'b101
|
| 673 |
|
|
`define alu_mode_afl 3'b110
|
| 674 |
|
|
`define alu_mode_afr 3'b111
|
| 675 |
|
|
|
| 676 |
|
|
// alu_op_a_sel
|
| 677 |
|
|
|
| 678 |
|
|
`define alu_op_a_00 3'b000
|
| 679 |
|
|
`define alu_op_a_acc 3'b001
|
| 680 |
|
|
`define alu_op_a_x 3'b010
|
| 681 |
|
|
`define alu_op_a_y 3'b011
|
| 682 |
|
|
`define alu_op_a_ff 3'b100
|
| 683 |
|
|
`define alu_op_a_psr 3'b101
|
| 684 |
|
|
|
| 685 |
|
|
// alu_op_b_sel
|
| 686 |
|
|
|
| 687 |
|
|
`define alu_op_b_00 2'b00
|
| 688 |
|
|
`define alu_op_b_prog 2'b01
|
| 689 |
|
|
`define alu_op_b_sp 2'b10
|
| 690 |
|
|
`define alu_op_b_temp 2'b11
|
| 691 |
|
|
|
| 692 |
|
|
// alu_op_b_inv 1=invert
|
| 693 |
|
|
|
| 694 |
|
|
|
| 695 |
|
|
|
| 696 |
|
|
// alu_op_c_sel
|
| 697 |
|
|
|
| 698 |
|
|
`define alu_op_c_00 2'b00
|
| 699 |
|
|
`define alu_op_c_01 2'b01
|
| 700 |
|
|
`define alu_op_c_cin 2'b10
|
| 701 |
|
|
`define alu_op_c_xx 2'b11
|
| 702 |
|
|
|
| 703 |
|
|
|
| 704 |
|
|
// alu_status_update
|
| 705 |
|
|
`define alu_status_update_none 3'b000
|
| 706 |
|
|
`define alu_status_update_nz 3'b001
|
| 707 |
|
|
`define alu_status_update_nzc 3'b010
|
| 708 |
|
|
`define alu_status_update_nzcv 3'b011
|
| 709 |
|
|
`define alu_status_update_wr 3'b100
|
| 710 |
|
|
`define alu_status_update_z67 3'b101
|
| 711 |
|
|
`define alu_status_update_res 3'b110
|
| 712 |
|
|
|
| 713 |
|
|
|
| 714 |
|
|
|
| 715 |
|
|
// dest
|
| 716 |
|
|
`define dest_none 3'b000
|
| 717 |
|
|
`define dest_alu_a 3'b001
|
| 718 |
|
|
`define dest_alu_x 3'b010
|
| 719 |
|
|
`define dest_alu_y 3'b011
|
| 720 |
|
|
`define dest_mem 3'b100
|
| 721 |
|
|
|
| 722 |
|
|
|
| 723 |
|
|
// ctrl
|
| 724 |
|
|
`define ctrl_none 3'b000
|
| 725 |
|
|
`define ctrl_jsr 3'b001
|
| 726 |
|
|
`define ctrl_jmp 3'b010
|
| 727 |
|
|
`define ctrl_jmp_ind 3'b011
|
| 728 |
|
|
`define ctrl_brk 3'b100
|
| 729 |
|
|
`define ctrl_rti 3'b101
|
| 730 |
|
|
`define ctrl_rts 3'b110
|
| 731 |
|
|
`define ctrl_branch 3'b111
|
| 732 |
|
|
|
| 733 |
|
|
// cmd
|
| 734 |
|
|
`define cmd_none 2'b00
|
| 735 |
|
|
`define cmd_push_psr 2'b01
|
| 736 |
|
|
`define cmd_push_pc 2'b10
|
| 737 |
|
|
`define cmd_load_vec 2'b11
|
| 738 |
|
|
|
| 739 |
|
|
|
| 740 |
|
|
// ins_type
|
| 741 |
|
|
`define ins_type_none 2'b00
|
| 742 |
|
|
`define ins_type_read 2'b01
|
| 743 |
|
|
`define ins_type_write 2'b10
|
| 744 |
|
|
`define ins_type_rmw 2'b11
|
| 745 |
|
|
|
| 746 |
|
|
|
| 747 |
|
|
// idx_sel
|
| 748 |
|
|
`define idx_sel_00 2'b00
|
| 749 |
|
|
`define idx_sel_x 2'b01
|
| 750 |
|
|
`define idx_sel_y 2'b10
|
| 751 |
|
|
|
| 752 |
|
|
|
| 753 |
|
|
|
| 754 |
|
|
// branch_value
|
| 755 |
|
|
|
| 756 |
|
|
|
| 757 |
|
|
// branch_enable
|
| 758 |
|
|
|
| 759 |
|
|
|
| 760 |
|
|
|
| 761 |
|
|
|
| 762 |
|
|
|
| 763 |
|
|
|
| 764 |
|
|
|
| 765 |
|
|
|
| 766 |
|
|
|
| 767 |
|
|
|
| 768 |
|
|
Immediate
|
| 769 |
|
|
|
| 770 |
|
|
alu alu alu alu alu
|
| 771 |
|
|
op_a op_b op_b op_c status alu ins idx branch branch
|
| 772 |
|
|
src src inv src update mode type sel value enable dest ctrl cmd
|
| 773 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 774 |
|
|
ADC #n | | alu_a prog 0 cin NZCV ADD R 0 00 00 A none none
|
| 775 |
|
|
AND #n | | alu_a prog 0 0 NZ AND R 0 00 00 A none none
|
| 776 |
|
|
CMP #n | | alu_a prog 1 1 NZC ADD R 0 00 00 0 none none
|
| 777 |
|
|
CPX #n | | alu_x prog 1 1 NZC ADD R 0 00 00 0 none none
|
| 778 |
|
|
CPY #n | | alu_y prog 1 1 NZC ADD R 0 00 00 0 none none
|
| 779 |
|
|
EOR #n | | alu_a prog 0 0 NZ EOR R 0 00 00 A none none
|
| 780 |
|
|
LDA #n | | 00 prog 0 0 NZ ADD R 0 00 00 A none none
|
| 781 |
|
|
LDX #n | | 00 prog 0 0 NZ ADD R 0 00 00 X none none
|
| 782 |
|
|
LDY #n | | 00 prog 0 0 NZ ADD R 0 00 00 Y none none
|
| 783 |
|
|
ORA #n | | alu_a prog 0 0 NZ ORR R 0 00 00 A none none
|
| 784 |
|
|
SBC #n | | alu_a prog 1 cin NZXV ADD R 0 00 00 A none none
|
| 785 |
|
|
|
| 786 |
|
|
|
| 787 |
|
|
|
| 788 |
|
|
|
| 789 |
|
|
Absolute
|
| 790 |
|
|
|
| 791 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 792 |
|
|
ADC abs | | alu_a temp 0 cin NZCV ADD R 0 00 00 A none none
|
| 793 |
|
|
AND abs | | alu_a temp 0 0 NZ AND R 0 00 00 A none none
|
| 794 |
|
|
BIT abs | | alu_a temp 0 0 Z67 AND R 0 00 00 0 none none
|
| 795 |
|
|
CMP abs | | alu_a temp 1 1 NZC ADD R 0 00 00 0 none none
|
| 796 |
|
|
CPX abs | | alu_x temp 1 1 NZC ADD R 0 00 00 0 none none
|
| 797 |
|
|
CPY abs | | alu_y temp 1 1 NZC ADD R 0 00 00 0 none none
|
| 798 |
|
|
EOR abs | | alu_a temp 0 0 NZ EOR R 0 00 00 A none none
|
| 799 |
|
|
LDA abs | | 00 temp 0 0 NZ ADD R 0 00 00 A none none
|
| 800 |
|
|
LDX abs | | 00 temp 0 0 NZ ADD R 0 00 00 X none none
|
| 801 |
|
|
LDY abs | | 00 temp 0 0 NZ ADD R 0 00 00 Y none none
|
| 802 |
|
|
ORA abs | | alu_a temp 0 0 NZ ORR R 0 00 00 A none none
|
| 803 |
|
|
SBC abs | | alu_a temp 1 cin NZXV ADD R 0 00 00 A none none
|
| 804 |
|
|
STA abs | | alu_a temp 0 0 NONE ADD W 0 00 00 M none none
|
| 805 |
|
|
STX abs | | alu_x temp 0 0 NONE ADD W 0 00 00 M none none
|
| 806 |
|
|
STY abs | | alu_y temp 0 0 NONE ADD W 0 00 00 M none none
|
| 807 |
|
|
ASL abs | | 00 temp 0 0 NZC SFL RMW 0 00 00 M none none
|
| 808 |
|
|
DEC abs | | FF temp 0 0 NZ ADD RMW 0 00 00 M none none
|
| 809 |
|
|
INC abs | | 00 temp 0 1 NZ ADD RMW 0 00 00 M none none
|
| 810 |
|
|
LSR abs | | 00 temp 0 0 NZC SFR RMW 0 00 00 M none none
|
| 811 |
|
|
ROL abs | | 00 temp 0 cin NZC SFL RMW 0 00 00 M none none
|
| 812 |
|
|
ROR abs | | 00 temp 0 cin NZC SFR RMW 0 00 00 M none none
|
| 813 |
|
|
|
| 814 |
|
|
|
| 815 |
|
|
Absolute indexed
|
| 816 |
|
|
|
| 817 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 818 |
|
|
ADC abs,X | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
|
| 819 |
|
|
AND abs,X | | alu_a temp 0 0 NZ AND R X 00 00 A none none
|
| 820 |
|
|
CMP abs,X | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
|
| 821 |
|
|
EOR abs,X | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
|
| 822 |
|
|
LDA abs,X | | 00 temp 0 0 NZ ADD R X 00 00 A none none
|
| 823 |
|
|
LDY abs,X | | 00 temp 0 0 NZ ADD R X 00 00 Y none none
|
| 824 |
|
|
ORA abs,X | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
|
| 825 |
|
|
SBC abs,X | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
|
| 826 |
|
|
ADC abs,Y | | alu_a temp 0 cin NZCV ADD R Y 00 00 A none none
|
| 827 |
|
|
AND abs,Y | | alu_a temp 0 0 NZ AND R Y 00 00 A none none
|
| 828 |
|
|
CMP abs,Y | | alu_a temp 1 1 NZC ADD R Y 00 00 0 none none
|
| 829 |
|
|
EOR abs,Y | | alu_a temp 0 0 NZ EOR R Y 00 00 A none none
|
| 830 |
|
|
LDA abs,Y | | 00 temp 0 0 NZ ADD R Y 00 00 A none none
|
| 831 |
|
|
LDX abs,Y | | 00 temp 0 0 NZ ADD R Y 00 00 X none none
|
| 832 |
|
|
ORA abs,Y | | alu_a temp 0 0 NZ ORR R Y 00 00 A none none
|
| 833 |
|
|
SBC abs,Y | | alu_a temp 1 cin NZXV ADD R Y 00 00 A none none
|
| 834 |
|
|
STA abs,X | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
|
| 835 |
|
|
STA abs,Y | | alu_a temp 0 0 NONE ADD W Y 00 00 M none none
|
| 836 |
|
|
ASL abs,X | | 00 temp 0 0 NZC SFL RMW X 00 00 M none none
|
| 837 |
|
|
DEC abs,X | | FF temp 0 0 NZ ADD RMW X 00 00 M none none
|
| 838 |
|
|
INC abs,X | | 00 temp 0 1 NZ ADD RMW X 00 00 M none none
|
| 839 |
|
|
LSR abs,X | | 00 temp 0 0 NZC SFR RMW X 00 00 M none none
|
| 840 |
|
|
ROL abs,X | | 00 temp 0 cin NZC SFL RMW X 00 00 M none none
|
| 841 |
|
|
ROR abs,X | | 00 temp 0 cin NZC SFR RMW X 00 00 M none none
|
| 842 |
|
|
|
| 843 |
|
|
|
| 844 |
|
|
|
| 845 |
|
|
|
| 846 |
|
|
|
| 847 |
|
|
|
| 848 |
|
|
Page Zero
|
| 849 |
|
|
|
| 850 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 851 |
|
|
ADC zp | | alu_a temp 0 cin NZCV ADD R 0 00 00 A none none
|
| 852 |
|
|
AND zp | | alu_a temp 0 0 NZ AND R 0 00 00 A none none
|
| 853 |
|
|
BIT zp | | alu_a temp 0 0 Z67 AND R 0 00 00 0 none none
|
| 854 |
|
|
CMP zp | | alu_a temp 1 1 NZC ADD R 0 00 00 0 none none
|
| 855 |
|
|
CPX zp | | alu_x temp 1 1 NZC ADD R 0 00 00 0 none none
|
| 856 |
|
|
CPY zp | | alu_y temp 1 1 NZC ADD R 0 00 00 0 none none
|
| 857 |
|
|
EOR zp | | alu_a temp 0 0 NZ EOR R 0 00 00 A none none
|
| 858 |
|
|
LDA zp | | 00 temp 0 0 NZ ADD R 0 00 00 A none none
|
| 859 |
|
|
LDX zp | | 00 temp 0 0 NZ ADD R 0 00 00 X none none
|
| 860 |
|
|
LDY zp | | 00 temp 0 0 NZ ADD R 0 00 00 Y none none
|
| 861 |
|
|
ORA zp | | alu_a temp 0 0 NZ ORR R 0 00 00 A none none
|
| 862 |
|
|
SBC zp | | alu_a temp 1 cin NZXV ADD R 0 00 00 A none none
|
| 863 |
|
|
STA zp | | alu_a temp 0 0 NONE ADD W 0 00 00 M none none
|
| 864 |
|
|
STX zp | | alu_x temp 0 0 NONE ADD W 0 00 00 M none none
|
| 865 |
|
|
STY zp | | alu_y temp 0 0 NONE ADD W 0 00 00 M none none
|
| 866 |
|
|
ASL zp | | 00 temp 0 0 NZC SFL RMW 0 00 00 M none none
|
| 867 |
|
|
DEC zp | | FF temp 0 0 NZ ADD RMW 0 00 00 M none none
|
| 868 |
|
|
INC zp | | 00 temp 0 1 NZ ADD RMW 0 00 00 M none none
|
| 869 |
|
|
LSR zp | | 00 temp 0 0 NZC SFR RMW 0 00 00 M none none
|
| 870 |
|
|
ROL zp | | 00 temp 0 cin NZC SFL RMW 0 00 00 M none none
|
| 871 |
|
|
ROR zp | | 00 temp 0 cin NZC SFR RMW 0 00 00 M none none
|
| 872 |
|
|
|
| 873 |
|
|
|
| 874 |
|
|
|
| 875 |
|
|
Page Zero indexed
|
| 876 |
|
|
|
| 877 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 878 |
|
|
ADC zp,X | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
|
| 879 |
|
|
AND zp,X | | alu_a temp 0 0 NZ AND R X 00 00 A none none
|
| 880 |
|
|
CMP zp,X | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
|
| 881 |
|
|
EOR zp,X | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
|
| 882 |
|
|
LDA zp,X | | 00 temp 0 0 NZ ADD R X 00 00 A none none
|
| 883 |
|
|
LDY zp,X | | 00 temp 0 0 NZ ADD R X 00 00 Y none none
|
| 884 |
|
|
ORA zp,X | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
|
| 885 |
|
|
SBC zp,X | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
|
| 886 |
|
|
LDX zp,Y | | 00 temp 0 0 NZ ADD R Y 00 00 X none none
|
| 887 |
|
|
STA zp,X | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
|
| 888 |
|
|
STY zp,X | | alu_y temp 0 0 NONE ADD W X 00 00 M none none
|
| 889 |
|
|
STX zp,Y | | alu_x temp 0 0 NONE ADD W Y 00 00 M none none
|
| 890 |
|
|
ASL zp,X | | 00 temp 0 0 NZC SFL RMW X 00 00 M none none
|
| 891 |
|
|
DEC zp,X | | FF temp 0 0 NZ ADD RMW X 00 00 M none none
|
| 892 |
|
|
INC zp,X | | 00 temp 0 1 NZ ADD RMW X 00 00 M none none
|
| 893 |
|
|
LSR zp,X | | 00 temp 0 0 NZC SFR RMW X 00 00 M none none
|
| 894 |
|
|
ROR zp,X | | 00 temp 0 cin NZC SFR RMW X 00 00 M none none
|
| 895 |
|
|
ROL zp,X | | 00 temp 0 cin NZC SFL RMW X 00 00 M none none
|
| 896 |
|
|
|
| 897 |
|
|
|
| 898 |
|
|
|
| 899 |
|
|
Page Zero indirectX
|
| 900 |
|
|
|
| 901 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 902 |
|
|
ADC (zp,X) | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
|
| 903 |
|
|
AND (zp,X) | | alu_a temp 0 0 NZ AND R X 00 00 A none none
|
| 904 |
|
|
CMP (zp,X) | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
|
| 905 |
|
|
EOR (zp,X) | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
|
| 906 |
|
|
LDA (zp,X) | | 00 temp 0 0 NZ ADD R X 00 00 A none none
|
| 907 |
|
|
ORA (zp,X) | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
|
| 908 |
|
|
SBC (zp,X) | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
|
| 909 |
|
|
STA (zp,X) | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
|
| 910 |
|
|
|
| 911 |
|
|
|
| 912 |
|
|
|
| 913 |
|
|
======================================================================================================================================================
|
| 914 |
|
|
|
| 915 |
|
|
|
| 916 |
|
|
Page Zero IndirectY
|
| 917 |
|
|
|
| 918 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 919 |
|
|
ADC (zp),Y | | alu_a temp 0 cin NZCV ADD R Y 00 00 A none none
|
| 920 |
|
|
AND (zp),Y | | alu_a temp 0 0 NZ AND R Y 00 00 A none none
|
| 921 |
|
|
CMP (zp),Y | | alu_a temp 1 1 NZC ADD R Y 00 00 0 none none
|
| 922 |
|
|
EOR (zp),Y | | alu_a temp 0 0 NZ EOR R Y 00 00 A none none
|
| 923 |
|
|
LDA (zp),Y | | 00 temp 0 0 NZ ADD R Y 00 00 A none none
|
| 924 |
|
|
ORA (zp),Y | | alu_a temp 0 0 NZ ORR R Y 00 00 A none none
|
| 925 |
|
|
SBC (zp),Y | | alu_a temp 1 cin NZXV ADD R Y 00 00 A none none
|
| 926 |
|
|
STA (zp),Y | | alu_a temp 0 0 NONE ADD W Y 00 00 M none none
|
| 927 |
|
|
|
| 928 |
|
|
|
| 929 |
|
|
|
| 930 |
|
|
|
| 931 |
|
|
|
| 932 |
|
|
Implied
|
| 933 |
|
|
|
| 934 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 935 |
|
|
NOP | | 00 00 0 0 NONE ADD 0 0 00 00 0 none none
|
| 936 |
|
|
SEC | | 00 00 0 0 WR ADD 0 0 01 01 0 none none
|
| 937 |
|
|
SED | | 00 00 0 0 WR ADD 0 0 08 08 0 none none
|
| 938 |
|
|
SEI | | 00 00 0 0 WR ADD 0 0 04 04 0 none none
|
| 939 |
|
|
CLC | | 00 00 0 0 WR ADD 0 0 00 01 0 none none
|
| 940 |
|
|
CLD | | 00 00 0 0 WR ADD 0 0 00 08 0 none none
|
| 941 |
|
|
CLI | | 00 00 0 0 WR ADD 0 0 00 04 0 none none
|
| 942 |
|
|
CLV | | 00 00 0 0 WR ADD 0 0 00 40 0 none none
|
| 943 |
|
|
ASL A | | alu_a 00 0 0 NZC SFL RMW 0 00 00 A none none
|
| 944 |
|
|
DEX | | alu_x 00 0 0 NZ ADD RMW 0 00 00 X none none
|
| 945 |
|
|
DEY | | alu_y 00 0 0 NZ ADD RMW 0 00 00 Y none none
|
| 946 |
|
|
INX | | alu_x 00 0 1 NZ ADD RMW 0 00 00 X none none
|
| 947 |
|
|
INY | | alu_y 00 0 1 NZ ADD RMW 0 00 00 Y none none
|
| 948 |
|
|
LSR A | | alu_a 00 0 0 NZC SFR RMW 0 00 00 A none none
|
| 949 |
|
|
ROL A | | alu_a 00 0 cin NZC SFL RMW 0 00 00 A none none
|
| 950 |
|
|
ROR A | | alu_a 00 0 cin NZC SFR RMW 0 00 00 A none none
|
| 951 |
|
|
TAX | | alu_a 00 0 0 NZ ADD RMW 0 00 00 A none none
|
| 952 |
|
|
TAY | | alu_a 00 0 0 NZ ADD RMW 0 00 00 X none none
|
| 953 |
|
|
TXA | | alu_x 00 0 0 NZ ADD RMW 0 00 00 A none none
|
| 954 |
|
|
TYA | | alu_y 00 0 0 NZ ADD RMW 0 00 00 A none none
|
| 955 |
|
|
|
| 956 |
|
|
|
| 957 |
|
|
|
| 958 |
|
|
Branch
|
| 959 |
|
|
alu alu alu alu alu
|
| 960 |
|
|
op_a op_b op_b op_c status alu branch branch
|
| 961 |
|
|
src src inv src update mode type index value enable dest
|
| 962 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 963 |
|
|
BCC rel | | 00 00 0 0 NONE ADD 0 0 00 01 0 branch none
|
| 964 |
|
|
BCS rel | | 00 00 0 0 NONE ADD 0 0 01 01 0 branch none
|
| 965 |
|
|
BNE rel | | 00 00 0 0 NONE ADD 0 0 00 02 0 branch none
|
| 966 |
|
|
BEQ rel | | 00 00 0 0 NONE ADD 0 0 02 02 0 branch none
|
| 967 |
|
|
BVC rel | | 00 00 0 0 NONE ADD 0 0 00 40 0 branch none
|
| 968 |
|
|
BVS rel | | 00 00 0 0 NONE ADD 0 0 40 40 0 branch none
|
| 969 |
|
|
BPL rel | | 00 00 0 0 NONE ADD 0 0 00 80 0 branch none
|
| 970 |
|
|
BMI rel | | 00 00 0 0 NONE ADD 0 0 80 80 0 branch none
|
| 971 |
|
|
|
| 972 |
|
|
|
| 973 |
|
|
|
| 974 |
|
|
Stack
|
| 975 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 976 |
|
|
PLA | | 00 00 0 0 NZ ADD R 0 00 00 A
|
| 977 |
|
|
PLP | | 00 00 0 0 RESTORE ADD R 0 00 00 PSR
|
| 978 |
|
|
PHA | | alu_a 00 0 0 NONE ADD W 0 00 00 M
|
| 979 |
|
|
PHP | | psr 00 0 0 NONE ADD W 0 00 00 M
|
| 980 |
|
|
|
| 981 |
|
|
|
| 982 |
|
|
|
| 983 |
|
|
Jump absolute
|
| 984 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 985 |
|
|
JMP abs | | 00 00 0 0 NONE ADD 0 0 00 00 0
|
| 986 |
|
|
|
| 987 |
|
|
|
| 988 |
|
|
|
| 989 |
|
|
Jump indirect
|
| 990 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 991 |
|
|
JMP (abs) | | 00 00 0 0 NONE ADD 0 0 00 00 0
|
| 992 |
|
|
|
| 993 |
|
|
|
| 994 |
|
|
|
| 995 |
|
|
Jump Sub absolute
|
| 996 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 997 |
|
|
JSR abs | | 00 00 0 0 NONE ADD 0 0 00 00 0
|
| 998 |
|
|
|
| 999 |
|
|
|
| 1000 |
|
|
|
| 1001 |
|
|
Break
|
| 1002 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 1003 |
|
|
BRK | | alu_a 00 0 0 WR ADD 0 0 10 10 0
|
| 1004 |
|
|
|
| 1005 |
|
|
|
| 1006 |
|
|
|
| 1007 |
|
|
Return from
|
| 1008 |
|
|
Interrupt
|
| 1009 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 1010 |
|
|
RTI | | 00 00 0 0 RESTORE ADD 0 0 00 00 P
|
| 1011 |
|
|
|
| 1012 |
|
|
|
| 1013 |
|
|
|
| 1014 |
|
|
Return from
|
| 1015 |
|
|
Subroutine
|
| 1016 |
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 1017 |
|
|
RTS | | 00 00 0 0 NONE ADD 0 0 00 00 0
|
| 1018 |
|
|
|
| 1019 |
|
|
|
| 1020 |
|
|
|
| 1021 |
|
|
|
| 1022 |
|
|
|
| 1023 |
|
|
|
| 1024 |
|
|
|
| 1025 |
|
|
|
| 1026 |
|
|
|
| 1027 |
|
|
|
| 1028 |
|
|
|
| 1029 |
|
|
|
| 1030 |
|
|
|
| 1031 |
|
|
|
| 1032 |
|
|
|
| 1033 |
|
|
|
| 1034 |
|
|
|
| 1035 |
|
|
|
| 1036 |
|
|
|
| 1037 |
|
|
|
| 1038 |
|
|
|
| 1039 |
|
|
|
| 1040 |
|
|
|
| 1041 |
|
|
|
| 1042 |
|
|
|
| 1043 |
|
|
|
| 1044 |
|
|
|
| 1045 |
|
|
|
| 1046 |
|
|
|
| 1047 |
|
|
Opcode Current Instruction byte
|
| 1048 |
|
|
New_opcode Next Instruction byte
|
| 1049 |
|
|
Opc_Add Address of current instruction
|
| 1050 |
|
|
Next_Op_Add Address of next instruction byte
|
| 1051 |
|
|
Operand Data operand
|
| 1052 |
|
|
Address Address of data operand if in memory
|
| 1053 |
|
|
Offset Value added to Opc_Add if branch is taken
|
| 1054 |
|
|
Pointer Address to store the address of data opeand if in memory
|
| 1055 |
|
|
Vector Address to store the Next_Op_Add
|
| 1056 |
|
|
|
| 1057 |
|
|
|
| 1058 |
|
|
|
| 1059 |
|
|
|
| 1060 |
|
|
|
| 1061 |
|
|
|
| 1062 |
|
|
|
| 1063 |
|
|
|
| 1064 |
|
|
|
| 1065 |
|
|
Address Sequence Decodes
|
| 1066 |
|
|
=========================================================================
|
| 1067 |
|
|
|
| 1068 |
|
|
|
| 1069 |
|
|
|
| 1070 |
|
|
|
| 1071 |
|
|
|
| 1072 |
|
|
|
| 1073 |
|
|
Implied Addressing Mode
|
| 1074 |
|
|
|
| 1075 |
|
|
c e ALU
|
| 1076 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1077 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1078 |
|
|
______________________________________________________________________________________________________________________________________
|
| 1079 |
|
|
|
| 1080 |
|
|
1 1 Opc_Add Opcode opcode
|
| 1081 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------
|
| 1082 |
|
|
2 0 Opc_Add+1 Opcode 1 Set
|
| 1083 |
|
|
3 1 Opc_Add+1 New_Opcode opcode 1 Set
|
| 1084 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------
|
| 1085 |
|
|
4 0 Opc_Add+2 New_Opcode updated
|
| 1086 |
|
|
|
| 1087 |
|
|
|
| 1088 |
|
|
|
| 1089 |
|
|
|
| 1090 |
|
|
Immediate Addressing Mode
|
| 1091 |
|
|
|
| 1092 |
|
|
|
| 1093 |
|
|
c e ALU
|
| 1094 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1095 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1096 |
|
|
____________________________________________________________________________________________________________________________________________________________
|
| 1097 |
|
|
|
| 1098 |
|
|
1 1 Opc_Add opcode opcode
|
| 1099 |
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------
|
| 1100 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1101 |
|
|
3 1 Opc_Add+1 operand operand Set
|
| 1102 |
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------
|
| 1103 |
|
|
4 0 Opc_Add+2 operand 1 Set
|
| 1104 |
|
|
5 1 Opc_Add+2 new_op opcode 1 Set
|
| 1105 |
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------
|
| 1106 |
|
|
6 0 Opc_Add+3 new_op updated
|
| 1107 |
|
|
|
| 1108 |
|
|
|
| 1109 |
|
|
|
| 1110 |
|
|
|
| 1111 |
|
|
|
| 1112 |
|
|
|
| 1113 |
|
|
|
| 1114 |
|
|
Absolute Read Addressing Mode
|
| 1115 |
|
|
|
| 1116 |
|
|
c e ALU
|
| 1117 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1118 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1119 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1120 |
|
|
|
| 1121 |
|
|
1 1 Opc_Add opcode opcode
|
| 1122 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1123 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1124 |
|
|
3 1 Opc_Add+2 add_lo add_lo Set
|
| 1125 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1126 |
|
|
4 0 Opc_Add+3 add_hi add_hi Set
|
| 1127 |
|
|
5 1 Opc_Add+3 new_op addr r 00 Set
|
| 1128 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1129 |
|
|
6 0 Opc_Add+3 new_op addr r 00 operand Set
|
| 1130 |
|
|
7 1 Opc_Add+3 new_op addr r 00 operand Set
|
| 1131 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1132 |
|
|
8 0 Opc_Add+3 new_op 1 Set
|
| 1133 |
|
|
9 1 Opc_Add+3 new_op opcode 1 Set
|
| 1134 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1135 |
|
|
10 0 updated
|
| 1136 |
|
|
|
| 1137 |
|
|
|
| 1138 |
|
|
|
| 1139 |
|
|
|
| 1140 |
|
|
|
| 1141 |
|
|
|
| 1142 |
|
|
Absolute Write Addressing Mode
|
| 1143 |
|
|
|
| 1144 |
|
|
c e ALU
|
| 1145 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1146 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1147 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1148 |
|
|
|
| 1149 |
|
|
1 1 Opc_Add opcode opcode
|
| 1150 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1151 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1152 |
|
|
3 1 Opc_Add+2 add_lo add_lo Set
|
| 1153 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1154 |
|
|
4 0 Opc_Add+3 add_hi add_hi Set
|
| 1155 |
|
|
5 1 Opc_Add+3 new_op opcode addr w operand 1 Set
|
| 1156 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1157 |
|
|
6 0 Opc_Add+4 new_op updated
|
| 1158 |
|
|
7 1 Opc_Add+4
|
| 1159 |
|
|
|
| 1160 |
|
|
|
| 1161 |
|
|
|
| 1162 |
|
|
|
| 1163 |
|
|
|
| 1164 |
|
|
Absolute Read/Modify/Write Addressing Mode
|
| 1165 |
|
|
|
| 1166 |
|
|
c e ALU
|
| 1167 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1168 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1169 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1170 |
|
|
|
| 1171 |
|
|
1 1 Opc_Add opcode opcode
|
| 1172 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1173 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1174 |
|
|
3 1 Opc_Add+2 add_lo add_lo Set
|
| 1175 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1176 |
|
|
4 0 Opc_Add+3 add_hi add_hi Set
|
| 1177 |
|
|
5 1 Opc_Add+3 new_op addr r Set
|
| 1178 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1179 |
|
|
6 0 Opc_Add+3 new_op operand Set
|
| 1180 |
|
|
7 1 Opc_Add+3 new_op Set
|
| 1181 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1182 |
|
|
8 0 Opc_Add+3 new_op addr w result 1 Set
|
| 1183 |
|
|
9 1 Opc_Add+3 new_op opcode 1 Set
|
| 1184 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1185 |
|
|
10 0 updated
|
| 1186 |
|
|
|
| 1187 |
|
|
|
| 1188 |
|
|
|
| 1189 |
|
|
|
| 1190 |
|
|
|
| 1191 |
|
|
|
| 1192 |
|
|
|
| 1193 |
|
|
Absolute Indexed Read Addressing Mode
|
| 1194 |
|
|
|
| 1195 |
|
|
c e ALU
|
| 1196 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1197 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1198 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1199 |
|
|
|
| 1200 |
|
|
1 1 Opc_Add opcode opcode
|
| 1201 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1202 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1203 |
|
|
3 1 Opc_Add+2 add_lo add_lo Set
|
| 1204 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1205 |
|
|
4 0 Opc_Add+3 add_hi add_hi Set
|
| 1206 |
|
|
5 1 Opc_Add+3 new_op addr+i r 00 Set
|
| 1207 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1208 |
|
|
6 0 Opc_Add+3 new_op addr+i r 00 operand Set
|
| 1209 |
|
|
7 1 Opc_Add+3 new_op addr+i r 00 operand Set
|
| 1210 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1211 |
|
|
8 0 Opc_Add+3 new_op 1 Set
|
| 1212 |
|
|
9 1 Opc_Add+3 new_op opcode 1 Set
|
| 1213 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1214 |
|
|
10 0 updated
|
| 1215 |
|
|
|
| 1216 |
|
|
|
| 1217 |
|
|
|
| 1218 |
|
|
Absolute Indexed Write Addressing Mode
|
| 1219 |
|
|
|
| 1220 |
|
|
c e ALU
|
| 1221 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1222 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1223 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1224 |
|
|
|
| 1225 |
|
|
1 1 Opc_Add opcode opcode
|
| 1226 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1227 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1228 |
|
|
3 1 Opc_Add+2 add_lo add_lo Set
|
| 1229 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1230 |
|
|
4 0 Opc_Add+3 add_hi add_hi 1 Set
|
| 1231 |
|
|
5 1 Opc_Add+3 new_op opcode addr+i w operand 1 Set
|
| 1232 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1233 |
|
|
6 0 Opc_Add+4 new_op updated
|
| 1234 |
|
|
7 1 Opc_Add+4
|
| 1235 |
|
|
|
| 1236 |
|
|
|
| 1237 |
|
|
|
| 1238 |
|
|
|
| 1239 |
|
|
|
| 1240 |
|
|
Absolute Indexed Read/Modify/Write Addressing Mode
|
| 1241 |
|
|
|
| 1242 |
|
|
c e ALU
|
| 1243 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1244 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1245 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1246 |
|
|
|
| 1247 |
|
|
1 1 Opc_Add opcode opcode
|
| 1248 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1249 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1250 |
|
|
3 1 Opc_Add+2 add_lo add_lo Set
|
| 1251 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1252 |
|
|
4 0 Opc_Add+3 add_hi add_hi Set
|
| 1253 |
|
|
5 1 Opc_Add+3 new_op addr+i r Set
|
| 1254 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1255 |
|
|
6 0 Opc_Add+3 new_op operand Set
|
| 1256 |
|
|
7 1 Opc_Add+3 new_op Set
|
| 1257 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1258 |
|
|
8 0 Opc_Add+3 new_op addr+i w result 1 Set
|
| 1259 |
|
|
9 1 Opc_Add+3 new_op opcode 1 Set
|
| 1260 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1261 |
|
|
10 0 updated
|
| 1262 |
|
|
|
| 1263 |
|
|
|
| 1264 |
|
|
|
| 1265 |
|
|
|
| 1266 |
|
|
|
| 1267 |
|
|
|
| 1268 |
|
|
|
| 1269 |
|
|
|
| 1270 |
|
|
|
| 1271 |
|
|
|
| 1272 |
|
|
|
| 1273 |
|
|
|
| 1274 |
|
|
Page Zero Read Addressing Mode
|
| 1275 |
|
|
|
| 1276 |
|
|
c e ALU
|
| 1277 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1278 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1279 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1280 |
|
|
|
| 1281 |
|
|
1 1 Opc_Add opcode opcode
|
| 1282 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1283 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1284 |
|
|
3 1 Opc_Add+1 add_lo add_lo Set
|
| 1285 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1286 |
|
|
4 0 Opc_Add+2 add_lo addr r Set
|
| 1287 |
|
|
5 1 Opc_Add+2 new_op operand Set
|
| 1288 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1289 |
|
|
6 0 Opc_Add+2 new_op 1 Set
|
| 1290 |
|
|
7 1 Opc_Add+2 new_op opcode 1 Set
|
| 1291 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1292 |
|
|
8 0 Opc_Add+3 new_op updated
|
| 1293 |
|
|
|
| 1294 |
|
|
|
| 1295 |
|
|
|
| 1296 |
|
|
|
| 1297 |
|
|
|
| 1298 |
|
|
|
| 1299 |
|
|
|
| 1300 |
|
|
|
| 1301 |
|
|
Page Zero Write Addressing Mode
|
| 1302 |
|
|
|
| 1303 |
|
|
c e ALU
|
| 1304 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1305 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1306 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1307 |
|
|
|
| 1308 |
|
|
1 1 Opc_Add opcode opcode
|
| 1309 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1310 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1311 |
|
|
3 1 Opc_Add+1 add_lo add_lo Set
|
| 1312 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1313 |
|
|
4 0 Opc_Add+2 add_lo 1 Set
|
| 1314 |
|
|
5 1 Opc_Add+2 new_op opcode addr w operand 1 Set
|
| 1315 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1316 |
|
|
6 0 Opc_Add+3 new_op updated
|
| 1317 |
|
|
7 1 Opc_Add+3
|
| 1318 |
|
|
|
| 1319 |
|
|
|
| 1320 |
|
|
|
| 1321 |
|
|
|
| 1322 |
|
|
|
| 1323 |
|
|
|
| 1324 |
|
|
|
| 1325 |
|
|
Page Zero Read/Modify/Write Addressing Mode
|
| 1326 |
|
|
|
| 1327 |
|
|
c e ALU
|
| 1328 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1329 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1330 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1331 |
|
|
|
| 1332 |
|
|
1 1 Opc_Add opcode opcode
|
| 1333 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1334 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1335 |
|
|
3 1 Opc_Add+1 add_lo add_lo Set
|
| 1336 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1337 |
|
|
4 0 Opc_Add+2 add_lo addr r Set
|
| 1338 |
|
|
5 1 Opc_Add+2 new_op operand Set
|
| 1339 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1340 |
|
|
6 0 Opc_Add+2 new_op 1 Set
|
| 1341 |
|
|
7 1 Opc_Add+2 new_op opcode addr w result 1 Set
|
| 1342 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1343 |
|
|
8 0 Opc_Add+3 new_op updated
|
| 1344 |
|
|
|
| 1345 |
|
|
|
| 1346 |
|
|
|
| 1347 |
|
|
|
| 1348 |
|
|
|
| 1349 |
|
|
|
| 1350 |
|
|
|
| 1351 |
|
|
|
| 1352 |
|
|
|
| 1353 |
|
|
|
| 1354 |
|
|
Page Zero Indexed Read Addressing Mode
|
| 1355 |
|
|
|
| 1356 |
|
|
c e ALU
|
| 1357 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1358 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1359 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1360 |
|
|
|
| 1361 |
|
|
1 1 Opc_Add opcode opcode
|
| 1362 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1363 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1364 |
|
|
3 1 Opc_Add+1 add_lo add_lo Set
|
| 1365 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1366 |
|
|
4 0 Opc_Add+2 add_lo addr+i r Set
|
| 1367 |
|
|
5 1 Opc_Add+2 new_op operand Set
|
| 1368 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1369 |
|
|
6 0 Opc_Add+2 new_op 1 Set
|
| 1370 |
|
|
7 1 Opc_Add+2 new_op opcode 1 Set
|
| 1371 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1372 |
|
|
8 0 Opc_Add+3 new_op updated
|
| 1373 |
|
|
|
| 1374 |
|
|
|
| 1375 |
|
|
|
| 1376 |
|
|
|
| 1377 |
|
|
|
| 1378 |
|
|
Page Zero Indexed Write Addressing Mode
|
| 1379 |
|
|
|
| 1380 |
|
|
c e ALU
|
| 1381 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1382 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1383 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1384 |
|
|
|
| 1385 |
|
|
1 1 Opc_Add opcode opcode
|
| 1386 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1387 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1388 |
|
|
3 1 Opc_Add+1 add_lo add_lo Set
|
| 1389 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1390 |
|
|
4 0 Opc_Add+2 add_lo 1 Set
|
| 1391 |
|
|
5 1 Opc_Add+2 new_op opcode addr w operand 1 Set
|
| 1392 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1393 |
|
|
6 0 Opc_Add+3 new_op updated
|
| 1394 |
|
|
7 1 Opc_Add+3
|
| 1395 |
|
|
|
| 1396 |
|
|
|
| 1397 |
|
|
|
| 1398 |
|
|
|
| 1399 |
|
|
|
| 1400 |
|
|
|
| 1401 |
|
|
|
| 1402 |
|
|
Page Zero Indexed Read/Modify/Write Addressing Mode
|
| 1403 |
|
|
|
| 1404 |
|
|
c e ALU
|
| 1405 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1406 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1407 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1408 |
|
|
|
| 1409 |
|
|
1 1 Opc_Add opcode opcode
|
| 1410 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1411 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1412 |
|
|
3 1 Opc_Add+1 add_lo add_lo Set
|
| 1413 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1414 |
|
|
4 0 Opc_Add+2 add_lo addr r Set
|
| 1415 |
|
|
5 1 Opc_Add+2 new_op operand Set
|
| 1416 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1417 |
|
|
6 0 Opc_Add+2 new_op 1 Set
|
| 1418 |
|
|
7 1 Opc_Add+2 new_op opcode addr w result 1 Set
|
| 1419 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1420 |
|
|
8 0 Opc_Add+3 new_op updated
|
| 1421 |
|
|
|
| 1422 |
|
|
|
| 1423 |
|
|
|
| 1424 |
|
|
|
| 1425 |
|
|
|
| 1426 |
|
|
|
| 1427 |
|
|
|
| 1428 |
|
|
|
| 1429 |
|
|
|
| 1430 |
|
|
|
| 1431 |
|
|
|
| 1432 |
|
|
|
| 1433 |
|
|
|
| 1434 |
|
|
|
| 1435 |
|
|
Page Zero Indirect X Read
|
| 1436 |
|
|
-------------------------------------------------------
|
| 1437 |
|
|
Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode and
|
| 1438 |
|
|
the upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)
|
| 1439 |
|
|
|
| 1440 |
|
|
|
| 1441 |
|
|
|
| 1442 |
|
|
|
| 1443 |
|
|
Page Zero IndirectX Read Addressing Mode
|
| 1444 |
|
|
|
| 1445 |
|
|
c e ALU
|
| 1446 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1447 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1448 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1449 |
|
|
|
| 1450 |
|
|
1 1 Opc_Add opcode opcode
|
| 1451 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1452 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1453 |
|
|
3 1 Opc_Add+1 add_lo add_lo Set
|
| 1454 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1455 |
|
|
4 0 Opc_Add+2 add_lo addr+i r Set
|
| 1456 |
|
|
5 1 Opc_Add+2 new_op addr+i+1 r add_l Set
|
| 1457 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1458 |
|
|
6 0 Opc_Add+2 new_op add_h Set
|
| 1459 |
|
|
7 1 Opc_Add+2 new_op addr r Set
|
| 1460 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1461 |
|
|
8 0 Opc_Add+2 new_op operand 1 Set
|
| 1462 |
|
|
9 1 opcode 1 Set
|
| 1463 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1464 |
|
|
10 0 updated
|
| 1465 |
|
|
|
| 1466 |
|
|
|
| 1467 |
|
|
|
| 1468 |
|
|
|
| 1469 |
|
|
|
| 1470 |
|
|
Page Zero IndirectX Write Addressing Mode
|
| 1471 |
|
|
|
| 1472 |
|
|
c e ALU
|
| 1473 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1474 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1475 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1476 |
|
|
|
| 1477 |
|
|
1 1 Opc_Add opcode opcode
|
| 1478 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1479 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1480 |
|
|
3 1 Opc_Add+1 add_lo add_lo Set
|
| 1481 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1482 |
|
|
4 0 Opc_Add+2 add_lo addr+i r Set
|
| 1483 |
|
|
5 1 Opc_Add+2 new_op addr+i+1 add_l Set
|
| 1484 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1485 |
|
|
6 0 Opc_Add+2 new_op add_h 1 Set
|
| 1486 |
|
|
7 1 Opc_Add+2 new_op opcode addr w result 1 Set
|
| 1487 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1488 |
|
|
8 0 Opc_Add+3 new_op updated
|
| 1489 |
|
|
9 1
|
| 1490 |
|
|
|
| 1491 |
|
|
|
| 1492 |
|
|
|
| 1493 |
|
|
|
| 1494 |
|
|
|
| 1495 |
|
|
|
| 1496 |
|
|
|
| 1497 |
|
|
|
| 1498 |
|
|
|
| 1499 |
|
|
Page Zero IndirectY Read Addressing Mode
|
| 1500 |
|
|
|
| 1501 |
|
|
c e ALU
|
| 1502 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1503 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1504 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1505 |
|
|
|
| 1506 |
|
|
1 1 Opc_Add opcode opcode
|
| 1507 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1508 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1509 |
|
|
3 1 Opc_Add+1 add_lo add_lo Set
|
| 1510 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1511 |
|
|
4 0 Opc_Add+2 add_lo addr_lo r Set
|
| 1512 |
|
|
5 1 Opc_Add+2 new_op addr Set
|
| 1513 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1514 |
|
|
6 0 Opc_Add+2 new_op addr+i r Set
|
| 1515 |
|
|
7 1 Opc_Add+2 new_op addr+i r operand Set
|
| 1516 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1517 |
|
|
8 0 Opc_Add+2 new_op 1 Set
|
| 1518 |
|
|
9 1 opcode 1 Set
|
| 1519 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1520 |
|
|
10 0 updated
|
| 1521 |
|
|
|
| 1522 |
|
|
|
| 1523 |
|
|
|
| 1524 |
|
|
|
| 1525 |
|
|
Page Zero IndirectX Write Addressing Mode
|
| 1526 |
|
|
|
| 1527 |
|
|
c e ALU
|
| 1528 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1529 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1530 |
|
|
___________________________________________________________________________________________________________________________________________________________
|
| 1531 |
|
|
|
| 1532 |
|
|
1 1 Opc_Add opcode opcode
|
| 1533 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1534 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1535 |
|
|
3 1 Opc_Add+1 add_lo add_lo Set
|
| 1536 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1537 |
|
|
4 0 Opc_Add+2 add_lo add_lo r 1 Set
|
| 1538 |
|
|
5 1 Opc_Add+2 new_op addr 1 Set
|
| 1539 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1540 |
|
|
6 0 Opc_Add+2 new_op addr+i w result Set
|
| 1541 |
|
|
7 1 Opc_Add+2 new_op opcode Set updated
|
| 1542 |
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
| 1543 |
|
|
8 0 Opc_Add+3 new_op
|
| 1544 |
|
|
9 1
|
| 1545 |
|
|
|
| 1546 |
|
|
|
| 1547 |
|
|
|
| 1548 |
|
|
|
| 1549 |
|
|
|
| 1550 |
|
|
|
| 1551 |
|
|
Relative Addressing Mode
|
| 1552 |
|
|
|
| 1553 |
|
|
|
| 1554 |
|
|
c e ALU
|
| 1555 |
|
|
l n prog prog prog data memory page zero stack Control Processsor
|
| 1556 |
|
|
k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
|
| 1557 |
|
|
____________________________________________________________________________________________________________________________________________________________
|
| 1558 |
|
|
|
| 1559 |
|
|
1 1 Opc_Add opcode opcode
|
| 1560 |
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------
|
| 1561 |
|
|
2 0 Opc_Add+1 opcode Set
|
| 1562 |
|
|
3 1 Opc_Add+1 offset offset Set
|
| 1563 |
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------
|
| 1564 |
|
|
4 0 Next_Op_Add offset 1
|
| 1565 |
|
|
5 1 Next_Op_Add new_op opcode 1
|
| 1566 |
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------
|
| 1567 |
|
|
6 0 Next_Op_Add+1 new_op
|
| 1568 |
|
|
|
| 1569 |
|
|
|
| 1570 |
|
|
|
| 1571 |
|
|
|
| 1572 |
|
|
|
| 1573 |
|
|
Addressing Modes
|
| 1574 |
|
|
===============================================================================================
|
| 1575 |
|
|
|
| 1576 |
|
|
|
| 1577 |
|
|
|
| 1578 |
|
|
|
| 1579 |
|
|
|
| 1580 |
|
|
Stack StackRead/StackWrite
|
| 1581 |
|
|
-------------------------------------------------------
|
| 1582 |
|
|
Operation uses the Stack
|
| 1583 |
|
|
|
| 1584 |
|
|
|
| 1585 |
|
|
|
| 1586 |
|
|
Jump Absolute Read
|
| 1587 |
|
|
-------------------------------------------------------
|
| 1588 |
|
|
16 bit destination address follows opcode
|
| 1589 |
|
|
|
| 1590 |
|
|
|
| 1591 |
|
|
Jump Indirect Read
|
| 1592 |
|
|
-------------------------------------------------------
|
| 1593 |
|
|
16 bit Address following opcode points to destination address
|
| 1594 |
|
|
|
| 1595 |
|
|
|
| 1596 |
|
|
|
| 1597 |
|
|
|
| 1598 |
|
|
Jump Sub Absolute Read_Stackwrite
|
| 1599 |
|
|
-------------------------------------------------------
|
| 1600 |
|
|
16 bit destination address follows opcode. Return address is pushed on stack
|
| 1601 |
|
|
|
| 1602 |
|
|
|
| 1603 |
|
|
|
| 1604 |
|
|
Break Read_Stackwrite
|
| 1605 |
|
|
-------------------------------------------------------
|
| 1606 |
|
|
Return address is pushed on stack and the IRQ vector is taken
|
| 1607 |
|
|
|
| 1608 |
|
|
|
| 1609 |
|
|
|
| 1610 |
|
|
Return from Interrupt Read_Stackread
|
| 1611 |
|
|
-------------------------------------------------------
|
| 1612 |
|
|
PSR and Prog_counter are pulled from stack
|
| 1613 |
|
|
|
| 1614 |
|
|
|
| 1615 |
|
|
|
| 1616 |
|
|
|
| 1617 |
|
|
Return from Subroutine Read_Stackread
|
| 1618 |
|
|
-------------------------------------------------------
|
| 1619 |
|
|
Prog_counter is pulled from stack
|
| 1620 |
|
|
|
| 1621 |
|
|
|
| 1622 |
|
|
|
| 1623 |
|
|
|
| 1624 |
|
|
|
| 1625 |
|
|
|
| 1626 |
|
|
|
| 1627 |
|
|
|
| 1628 |
|
|
|
| 1629 |
|
|
|
| 1630 |
|
|
|
| 1631 |
|
|
|
| 1632 |
|
|
|
| 1633 |
|
|
Interrupts
|
| 1634 |
|
|
===============================================================================================
|
| 1635 |
|
|
|
| 1636 |
|
|
Non-Maskable (NMI)
|
| 1637 |
|
|
|
| 1638 |
|
|
1) Finish current instruction
|
| 1639 |
|
|
2) Push Address of next instruction on stack
|
| 1640 |
|
|
3) Read Vector Address from FFFA
|
| 1641 |
|
|
4) Execute code @ vector address
|
| 1642 |
|
|
|
| 1643 |
|
|
|
| 1644 |
|
|
|
| 1645 |
|
|
Maskable (IRQ) ( if I bit is clear)
|
| 1646 |
|
|
|
| 1647 |
|
|
1) Finish current instruction
|
| 1648 |
|
|
2) Push Address of next instruction on stack
|
| 1649 |
|
|
3) Push PSR on stack
|
| 1650 |
|
|
4) Read Vector Address from FFFE
|
| 1651 |
|
|
5) Execute code @ vector address
|
| 1652 |
|
|
|
| 1653 |
|
|
|
| 1654 |
|
|
Reset
|
| 1655 |
|
|
|
| 1656 |
|
|
1) Clear A,X,Y: Set PSR to 20h
|
| 1657 |
|
|
2) Wait for Reset to deassert
|
| 1658 |
|
|
3) Read Vector Address from FFFC
|
| 1659 |
|
|
4) Execute code @ vector address
|
| 1660 |
|
|
|
| 1661 |
|
|
|
| 1662 |
|
|
|
| 1663 |
|
|
|
| 1664 |
|
|
|
| 1665 |
|
|
|
| 1666 |
|
|
|
| 1667 |
|
|
|
| 1668 |
|
|
|
| 1669 |
|
|
|
| 1670 |
|
|
|
| 1671 |
|
|
|
| 1672 |
|
|
|
| 1673 |
|
|
|
| 1674 |
|
|
|
| 1675 |
|
|
|
| 1676 |
|
|
|
| 1677 |
|
|
|
| 1678 |
|
|
|
| 1679 |
|
|
|
| 1680 |
|
|
|
| 1681 |
|
|
|
| 1682 |
|
|
|
| 1683 |
|
|
|
| 1684 |
|
|
|
| 1685 |
|
|
|
| 1686 |
|
|
|
| 1687 |
|
|
|
| 1688 |
|
|
|
| 1689 |
|
|
|
