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[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [syn/] [chips/] [xml/] [logipi_fpga_padring.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
valentfx.com
fpgas
logipi_T6502
padring
 

 
 
 
 

  gen_ise_filelist
  104.0
  none
  
    :*Synthesis:*
  
  tools/sys/gen_child_filelist
  
    
      top
    
    
      suffix
      ISE
    
    
      leader
      "verilog work "
    
    
      overlay_src_ven
      opencores.org
    
    
      overlay_src_lib
      cde
    
    
      overlay_des_ven
      valentfx.com
    
    
      overlay_des_lib
      logipi
    
 
  

 
 

 
 
 
 
 
 
 
 
 
 A_CLK
  
  
      
  
    
          
          PAD_in
          
          A_CLK
          
          
    
 
        
      
  
 
 
 
 
 
 
 SW
  
 
  
      
  
    
          
          PAD_in
          
          SW
          10
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 BTN
  
 
  
      
  
    
          
          PAD_in
          
          BTN
          10
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 LED
  
 
  
      
  
    
          
          PAD_out
          
          LED
          10
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 PMOD1
  
 
  
      
  
    
          
          PAD_io
          
          PMOD1
          70
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 
 PMOD2
  
 
  
      
  
    
          
          PAD_out
          
          PMOD2
          70
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 
 PMOD3
  
 
  
      
  
    
          
          PAD_out
          
          PMOD3
          70
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 
 PMOD4
  
 
  
      
  
    
          
          PAD_out
          
          PMOD4
          70
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 SYS_SPI_SCK
  
 
  
      
  
    
          
          PAD_in
          
          SYS_SPI_SCK
          
          
    
 
        
      
 
 
  
 
 
 
 
  SYS_SPI_MISO
  
 
  
      
  
    
          
          PAD_out
          
          SYS_SPI_MISO
          
          
    
 
        
      
 
 
  
 
 
 
 
 
  SYS_SPI_MOSI
  
 
  
      
  
    
          
          PAD_in
          
          SYS_SPI_MOSI
          
          
    
 
        
      
 
 
  
 
 
 
 
 
  RP_SPI_CE0N
  
 
  
      
  
    
          
          PAD_in
          
          RP_SPI_CE0N
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 

    CLOCK_PLL_MULT2
    CLOCK_PLL_DIV4
    CLOCK_PLL_SIZE4
    CLOCK_SRC0
    RESET_SENSE1
    CHIP_ID32'hf1c2e093

 
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
 
 
  
 
    
       Hierarchical
            Hierarchical
 
    
 
    
       pad
 
       Verilog
       
       fs-pad
    
 
  
 
 
 

 
 
A_CLK
wire
in

 
 
 SW
wire
in
 
 
 BTN
wire
in
 
 
 LED
wire
out
 
 
 PMOD1
wire
inout
 
 
 PMOD2
wire
inout
 
 
 PMOD3
wire
inout
 
 
 PMOD4
wire
inout
 
 
 SYS_SPI_SCK
wire
in
 
 
  SYS_SPI_MISO
wire
out
  
 
  SYS_SPI_MOSI
wire
in
  
 
  RP_SPI_CE0N
wire
in

 
 
 
 
 
 

 
 
 
 
 
 

 
 
 
 
 
 
 

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [syn/] [chips/] [xml/] [logipi_fpga_padring.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`valentfx.com`
37			`fpgas`
38			`logipi_T6502`
39			`padring`
40
41
42
43
44
45
46
47			`gen_ise_filelist`
48			`104.0`
49			`none`
50
51			`:Synthesis:`
52
53			`tools/sys/gen_child_filelist`
54
55
56			`top`
57
58
59			`suffix`
60			`ISE`
61
62
63			`leader`
64			`"verilog work "`
65
66
67			`overlay_src_ven`
68			`opencores.org`
69
70
71			`overlay_src_lib`
72			`cde`
73
74
75			`overlay_des_ven`
76			`valentfx.com`
77
78
79			`overlay_des_lib`
80			`logipi`
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97			`A_CLK`
98
99
100
101
102
103
104			`PAD_in`
105
106			`A_CLK`
107
108
109
110
111
112
113
114
115
116
117
118
119
120			`SW`
121
122
123
124
125
126
127
128			`PAD_in`
129
130			`SW`
131			`10`
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147			`BTN`
148
149
150
151
152
153
154
155			`PAD_in`
156
157			`BTN`
158			`10`
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174			`LED`
175
176
177
178
179
180
181
182			`PAD_out`
183
184			`LED`
185			`10`
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201			`PMOD1`
202
203
204
205
206
207
208
209			`PAD_io`
210
211			`PMOD1`
212			`70`
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229			`PMOD2`
230
231
232
233
234
235
236
237			`PAD_out`
238
239			`PMOD2`
240			`70`
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257			`PMOD3`
258
259
260
261
262
263
264
265			`PAD_out`
266
267			`PMOD3`
268			`70`
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285			`PMOD4`
286
287
288
289
290
291
292
293			`PAD_out`
294
295			`PMOD4`
296			`70`
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311			`SYS_SPI_SCK`
312
313
314
315
316
317
318
319			`PAD_in`
320
321			`SYS_SPI_SCK`
322
323
324
325
326
327
328
329
330
331
332
333
334
335			`SYS_SPI_MISO`
336
337
338
339
340
341
342
343			`PAD_out`
344
345			`SYS_SPI_MISO`
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360			`SYS_SPI_MOSI`
361
362
363
364
365
366
367
368			`PAD_in`
369
370			`SYS_SPI_MOSI`
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385			`RP_SPI_CE0N`
386
387
388
389
390
391
392
393			`PAD_in`
394
395			`RP_SPI_CE0N`
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437			`CLOCK_PLL_MULT2`
438			`CLOCK_PLL_DIV4`
439			`CLOCK_PLL_SIZE4`
440			`CLOCK_SRC0`
441			`RESET_SENSE1`
442			`CHIP_ID32'hf1c2e093`
443
444
445
446
447
448
449			`Hierarchical`
450
451
452
453
454
455
456
457
458
459
460
461
462			`Hierarchical`
463			`Hierarchical`
464
465
466
467
468			`pad`
469
470			`Verilog`
471
472			`fs-pad`
473
474
475
476
477
478
479
480
481
482			`A_CLK`
483			`wire`
484			`in`
485
486
487
488			`SW`
489			`wire`
490			`in`
491
492
493			`BTN`
494			`wire`
495			`in`
496
497
498			`LED`
499			`wire`
500			`out`
501
502
503			`PMOD1`
504			`wire`
505			`inout`
506
507
508			`PMOD2`
509			`wire`
510			`inout`
511
512
513			`PMOD3`
514			`wire`
515			`inout`
516
517
518			`PMOD4`
519			`wire`
520			`inout`
521
522
523			`SYS_SPI_SCK`
524			`wire`
525			`in`
526
527
528			`SYS_SPI_MISO`
529			`wire`
530			`out`
531
532
533			`SYS_SPI_MOSI`
534			`wire`
535			`in`
536
537
538			`RP_SPI_CE0N`
539			`wire`
540			`in`
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562