URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [AND/] [demorgan/] [and4.sym] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20031231 1`
2			`L 300 700 600 700 3 0 0 0 -1 -1`
3			`L 300 100 600 100 3 0 0 0 -1 -1`
4			`A 40 400 400 312 97 3 0 0 0 -1 -1`
5			`A 600 500 400 270 76 3 0 0 0 -1 -1`
6			`A 600 300 400 14 76 3 0 0 0 -1 -1`
7			`L 300 700 300 800 3 0 0 0 -1 -1`
8			`L 300 100 300 0 3 0 0 0 -1 -1`
9			`V 1050 400 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
10			`P 1100 400 1300 400 1 0 1`
11			`{`
12			`T 1000 400 5 8 0 0 0 0 1`
13			`pinnumber=OUT`
14			`T 1000 400 5 8 0 0 0 0 1`
15			`pinseq=1`
16			`}`
17			`V 250 100 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
18			`P 200 100 0 100 1 0 1`
19			`{`
20			`T 300 100 5 8 0 0 0 0 1`
21			`pinnumber=IN0`
22			`T 300 100 5 8 0 0 0 0 1`
23			`pinseq=2`
24			`}`
25			`V 250 300 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
26			`P 200 300 0 300 1 0 1`
27			`{`
28			`T 300 300 5 8 0 0 0 0 1`
29			`pinnumber=IN1`
30			`T 300 300 5 8 0 0 0 0 1`
31			`pinseq=3`
32			`}`
33			`V 250 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
34			`P 200 500 0 500 1 0 1`
35			`{`
36			`T 300 500 5 8 0 0 0 0 1`
37			`pinnumber=IN2`
38			`T 300 500 5 8 0 0 0 0 1`
39			`pinseq=4`
40			`}`
41			`V 250 700 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
42			`P 200 700 0 700 1 0 1`
43			`{`
44			`T 300 700 5 8 0 0 0 0 1`
45			`pinnumber=IN3`
46			`T 300 700 5 8 0 0 0 0 1`
47			`pinseq=5`
48			`}`
49			`T 400 0 5 10 1 1 0 2 1`
50			`refdes=U?`
51			`T 400 100 5 8 0 0 0 0 1`
52			`device=and`
53			`T 400 200 5 8 0 0 0 0 1`
54			`VERILOG_PORTS=POSITIONAL`