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[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [NOR/] [nor5.sym] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20031231 1`
2			`L 300 800 600 800 3 0 0 0 -1 -1`
3			`L 300 200 600 200 3 0 0 0 -1 -1`
4			`A 40 500 400 312 97 3 0 0 0 -1 -1`
5			`A 600 600 400 270 76 3 0 0 0 -1 -1`
6			`A 600 400 400 14 76 3 0 0 0 -1 -1`
7			`L 300 800 300 1000 3 0 0 0 -1 -1`
8			`L 300 200 300 0 3 0 0 0 -1 -1`
9			`V 1050 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
10			`P 1100 500 1300 500 1 0 1`
11			`{`
12			`T 1000 500 5 8 0 0 0 0 1`
13			`pinnumber=OUT`
14			`T 1000 500 5 8 0 0 0 0 1`
15			`pinseq=1`
16			`}`
17			`P 300 100 0 100 1 0 1`
18			`{`
19			`T 300 100 5 8 0 0 0 0 1`
20			`pinnumber=IN0`
21			`T 300 100 5 8 0 0 0 0 1`
22			`pinseq=2`
23			`}`
24			`P 300 300 0 300 1 0 1`
25			`{`
26			`T 300 300 5 8 0 0 0 0 1`
27			`pinnumber=IN1`
28			`T 300 300 5 8 0 0 0 0 1`
29			`pinseq=3`
30			`}`
31			`P 300 500 0 500 1 0 1`
32			`{`
33			`T 300 500 5 8 0 0 0 0 1`
34			`pinnumber=IN2`
35			`T 300 500 5 8 0 0 0 0 1`
36			`pinseq=4`
37			`}`
38			`P 300 700 0 700 1 0 1`
39			`{`
40			`T 300 700 5 8 0 0 0 0 1`
41			`pinnumber=IN3`
42			`T 300 700 5 8 0 0 0 0 1`
43			`pinseq=5`
44			`}`
45			`P 300 900 0 900 1 0 1`
46			`{`
47			`T 300 900 5 8 0 0 0 0 1`
48			`pinnumber=IN4`
49			`T 300 900 5 8 0 0 0 0 1`
50			`pinseq=6`
51			`}`
52			`T 400 100 5 10 1 1 0 2 1`
53			`refdes=U?`
54			`T 400 100 5 8 0 0 0 0 1`
55			`device=nor`
56			`T 400 200 5 8 0 0 0 0 1`
57			`VERILOG_PORTS=POSITIONAL`