URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [OR/] [demorgan/] [or4.sym] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20031231 1`
2			`L 300 700 700 700 3 0 0 0 -1 -1`
3			`L 300 100 700 100 3 0 0 0 -1 -1`
4			`L 300 100 300 700 3 0 0 0 -1 -1`
5			`A 700 400 300 270 180 3 0 0 0 -1 -1`
6			`L 300 700 300 800 3 0 0 0 -1 -1`
7			`L 300 100 300 0 3 0 0 0 -1 -1`
8			`V 1050 400 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
9			`P 1100 400 1300 400 1 0 1`
10			`{`
11			`T 1000 400 5 8 0 0 0 0 1`
12			`pinnumber=OUT`
13			`T 1000 400 5 8 0 0 0 0 1`
14			`pinseq=1`
15			`}`
16			`V 250 100 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
17			`P 200 100 0 100 1 0 1`
18			`{`
19			`T 300 100 5 8 0 0 0 0 1`
20			`pinnumber=IN0`
21			`T 300 100 5 8 0 0 0 0 1`
22			`pinseq=2`
23			`}`
24			`V 250 300 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
25			`P 200 300 0 300 1 0 1`
26			`{`
27			`T 300 300 5 8 0 0 0 0 1`
28			`pinnumber=IN1`
29			`T 300 300 5 8 0 0 0 0 1`
30			`pinseq=3`
31			`}`
32			`V 250 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
33			`P 200 500 0 500 1 0 1`
34			`{`
35			`T 300 500 5 8 0 0 0 0 1`
36			`pinnumber=IN2`
37			`T 300 500 5 8 0 0 0 0 1`
38			`pinseq=4`
39			`}`
40			`V 250 700 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
41			`P 200 700 0 700 1 0 1`
42			`{`
43			`T 300 700 5 8 0 0 0 0 1`
44			`pinnumber=IN3`
45			`T 300 700 5 8 0 0 0 0 1`
46			`pinseq=5`
47			`}`
48			`T 400 0 5 10 1 1 0 2 1`
49			`refdes=U?`
50			`T 400 100 5 8 0 0 0 0 1`
51			`device=or`
52			`T 400 200 5 8 0 0 0 0 1`
53			`VERILOG_PORTS=POSITIONAL`