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[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [OR/] [demorgan/] [or7.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20031231 1
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{
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pinnumber=OUT
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pinseq=1
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}
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{
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pinnumber=IN0
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pinseq=2
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}
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P 200 300 0 300 1 0 1
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{
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pinnumber=IN1
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pinseq=3
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}
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{
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pinnumber=IN2
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pinseq=4
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}
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{
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pinnumber=IN3
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pinseq=5
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}
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{
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pinnumber=IN4
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pinseq=6
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}
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{
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T 300 1100 5 8 0 0 0 0 1
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pinnumber=IN5
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pinseq=7
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}
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P 200 1300 0 1300 1 0 1
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{
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T 300 1300 5 8 0 0 0 0 1
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pinnumber=IN6
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T 300 1300 5 8 0 0 0 0 1
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pinseq=8
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}
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T 400 300 5 10 1 1 0 2 1
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refdes=U?
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device=or
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VERILOG_PORTS=POSITIONAL

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