URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [XNOR/] [xnor5.sym] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20031231 1`
2			`L 400 800 600 800 3 0 0 0 -1 -1`
3			`L 400 200 600 200 3 0 0 0 -1 -1`
4			`A 40 500 400 312 97 3 0 0 0 -1 -1`
5			`A 140 500 400 312 97 3 0 0 0 -1 -1`
6			`A 600 600 400 270 76 3 0 0 0 -1 -1`
7			`A 600 400 400 14 76 3 0 0 0 -1 -1`
8			`L 300 800 300 1000 3 0 0 0 -1 -1`
9			`L 300 200 300 0 3 0 0 0 -1 -1`
10			`V 1050 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
11			`P 1100 500 1300 500 1 0 1`
12			`{`
13			`T 1000 500 5 8 0 0 0 0 1`
14			`pinnumber=OUT`
15			`T 1000 500 5 8 0 0 0 0 1`
16			`pinseq=1`
17			`}`
18			`P 300 100 0 100 1 0 1`
19			`{`
20			`T 300 100 5 8 0 0 0 0 1`
21			`pinnumber=IN0`
22			`T 300 100 5 8 0 0 0 0 1`
23			`pinseq=2`
24			`}`
25			`P 300 300 0 300 1 0 1`
26			`{`
27			`T 300 300 5 8 0 0 0 0 1`
28			`pinnumber=IN1`
29			`T 300 300 5 8 0 0 0 0 1`
30			`pinseq=3`
31			`}`
32			`P 300 500 0 500 1 0 1`
33			`{`
34			`T 300 500 5 8 0 0 0 0 1`
35			`pinnumber=IN2`
36			`T 300 500 5 8 0 0 0 0 1`
37			`pinseq=4`
38			`}`
39			`P 300 700 0 700 1 0 1`
40			`{`
41			`T 300 700 5 8 0 0 0 0 1`
42			`pinnumber=IN3`
43			`T 300 700 5 8 0 0 0 0 1`
44			`pinseq=5`
45			`}`
46			`P 300 900 0 900 1 0 1`
47			`{`
48			`T 300 900 5 8 0 0 0 0 1`
49			`pinnumber=IN4`
50			`T 300 900 5 8 0 0 0 0 1`
51			`pinseq=6`
52			`}`
53			`T 400 100 5 10 1 1 0 2 1`
54			`refdes=U?`
55			`T 400 100 5 8 0 0 0 0 1`
56			`device=xnor`
57			`T 400 200 5 8 0 0 0 0 1`
58			`VERILOG_PORTS=POSITIONAL`