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[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [XOR/] [xor2.sym] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20031231 1`
2			`L 400 600 600 600 3 0 0 0 -1 -1`
3			`L 400 0 600 0 3 0 0 0 -1 -1`
4			`A 40 300 400 312 97 3 0 0 0 -1 -1`
5			`A 140 300 400 312 97 3 0 0 0 -1 -1`
6			`A 600 400 400 270 76 3 0 0 0 -1 -1`
7			`A 600 200 400 14 76 3 0 0 0 -1 -1`
8			`P 1000 300 1300 300 1 0 1`
9			`{`
10			`T 1000 300 5 8 0 0 0 0 1`
11			`pinnumber=OUT`
12			`T 1000 300 5 8 0 0 0 0 1`
13			`pinseq=1`
14			`}`
15			`P 300 100 0 100 1 0 1`
16			`{`
17			`T 300 100 5 8 0 0 0 0 1`
18			`pinnumber=IN0`
19			`T 300 100 5 8 0 0 0 0 1`
20			`pinseq=2`
21			`}`
22			`P 300 500 0 500 1 0 1`
23			`{`
24			`T 300 500 5 8 0 0 0 0 1`
25			`pinnumber=IN1`
26			`T 300 500 5 8 0 0 0 0 1`
27			`pinseq=3`
28			`}`
29			`T 400 -100 5 10 1 1 0 2 1`
30			`refdes=U?`
31			`T 400 100 5 8 0 0 0 0 1`
32			`device=xor`
33			`T 400 200 5 8 0 0 0 0 1`
34			`VERILOG_PORTS=POSITIONAL`