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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [rtl/] [verilog/] [clock_gen_syn] - Blame information for rev 134

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always@(posedge clk or negedge START)
  if(!START)  FINISH <= 0;
  else        FINISH <= (|STOP) || FINISH;
 
 
 
always@(posedge clk or negedge START)
  if(!START)  FAIL <= 0;
  else        FAIL <= (|BAD);
 
 
always@(posedge clk or negedge START)
  if(!START)  reset <= 1'b1;
  else        reset <= 1'b0;
 

Line No.	Rev	Author	Line
1	134	jt_eaton
2			`always@(posedge clk or negedge START)`
3			`if(!START) FINISH <= 0;`
4			`else FINISH <= (\|STOP) \|\| FINISH;`
5
6
7
8			`always@(posedge clk or negedge START)`
9			`if(!START) FAIL <= 0;`
10			`else FAIL <= (\|BAD);`
11
12
13			`always@(posedge clk or negedge START)`
14			`if(!START) reset <= 1'b1;`
15			`else reset <= 1'b0;`
16

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [rtl/] [verilog/] [clock_gen_syn] - Blame information for rev 134