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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [rtl/] [xml/] [clock_gen_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
clock_gen
def  default
 
 

 
 
 
 master_clk
  
  
  
    
      
        clk
        clk
reg

      
 
    
 
 
 
 
 
 master_reset
  
  
  
    
      
        reset
        reset
reg

      
    
 
 
 
 

 
 
 
 
 
 
  
      fs-sim
 
      
        dest_dir
        ../verilog/sim/
        verilogSourcelibraryDir
      
 
    
 
 
    
    fs-syn
 
     
        dest_dir
        ../verilog/syn/
        verilogSourcelibraryDir
      
 
    
 
  
 
 
 

       
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
  
 
 STOP_WIDTH1
 BAD_WIDTH1

 
 

 
START
wire
in

 
STOP
wire
inSTOP_WIDTH-10

 
BAD
wire
inBAD_WIDTH-10

 
FAIL
reg
out

 
 
FINISH
reg
out

 

 
 
 
 
 
 

 
 
 
 
 
 
 
 
 

 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`clock_gen`
40			`def default`
41
42
43
44
45
46
47			`master_clk`
48
49
50
51
52
53			`clk`
54			`clk`
55			`reg`
56
57
58
59
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61
62
63
64
65			`master_reset`
66
67
68
69
70
71			`reset`
72			`reset`
73			`reg`
74
75
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80
81
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83
84
85
86
87
88
89			`fs-sim`
90
91
92			`dest_dir`
93			`../verilog/sim/`
94			`verilogSourcelibraryDir`
95
96
97
98
99
100
101			`fs-syn`
102
103
104			`dest_dir`
105			`../verilog/syn/`
106			`verilogSourcelibraryDir`
107
108
109
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111
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115
116
117
118
119			`sim:Simulation:`
120			`Verilog`
121
122
123			`fs-sim`
124
125
126
127
128			`syn:Synthesis:`
129			`Verilog`
130
131
132			`fs-syn`
133
134
135
136
137			`doc`
138
139
140			`spirit:library="Testbench"`
141			`spirit:name="toolflow"`
142			`spirit:version="documentation"/>`
143
144			`:Documentation:`
145			`Verilog`
146
147
148
149
150
151
152
153			`STOP_WIDTH1`
154			`BAD_WIDTH1`
155
156
157
158
159
160			`START`
161			`wire`
162			`in`
163
164
165			`STOP`
166			`wire`
167			`inSTOP_WIDTH-10`
168
169
170			`BAD`
171			`wire`
172			`inBAD_WIDTH-10`
173
174
175			`FAIL`
176			`reg`
177			`out`
178
179
180
181			`FINISH`
182			`reg`
183			`out`
184
185
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191
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [rtl/] [xml/] [clock_gen_def.xml] - Blame information for rev 131