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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [rtl/] [xml/] [clock_gen_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
clock_gen
def  default
 
 

 
 
 
 master_clk
  
  
  
    
      
        clk
        clk
reg

      
 
    
 
 
 
 
 
 master_reset
  
  
  
    
      
        reset
        reset
reg

      
    
 
 
 
 

 
 
 

 
 
 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  
 

 
 
 

  gen_design
  103.0
  none
  :*Simulation:*
  ./tools/verilog/gen_design
    
    
      dest_dir
      io_ports
    
  
 

 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
      fs-sim
 
      
        dest_dir
        ../verilog/sim/
        verilogSourcelibraryDir
      
 
    
 
 
    
    fs-syn
 
     
        dest_dir
        ../verilog/syn/
        verilogSourcelibraryDir
      
 
    
 
  
 
 
 

       
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
  
 
 STOP_WIDTH1
 BAD_WIDTH1

 
 

 
START
wire
in

 
STOP
wire
inSTOP_WIDTH-10

 
BAD
wire
inBAD_WIDTH-10

 
FAIL
reg
out

 
 
FINISH
reg
out

 

 
 
 
 
 
 

 
 
 
 
 
 
 
 
 

 
 

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [rtl/] [xml/] [clock_gen_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`clock_gen`
40			`def default`
41
42
43
44
45
46
47			`master_clk`
48
49
50
51
52
53			`clk`
54			`clk`
55			`reg`
56
57
58
59
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61
62
63
64
65			`master_reset`
66
67
68
69
70
71			`reset`
72			`reset`
73			`reg`
74
75
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77
78
79
80
81
82
83
84
85	133	jt_eaton
86
87
88
89
90			`elab_verilog`
91			`103.0`
92			`none`
93			`:Simulation:`
94			`./tools/verilog/elab_verilog`
95
96
97			`dest_dir`
98			`io_ports`
99
100
101
102
103
104
105
106
107			`gen_design`
108			`103.0`
109			`none`
110			`:Simulation:`
111			`./tools/verilog/gen_design`
112
113
114			`dest_dir`
115			`io_ports`
116
117
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135	131	jt_eaton
136
137
138
139			`fs-sim`
140
141
142			`dest_dir`
143			`../verilog/sim/`
144			`verilogSourcelibraryDir`
145
146
147
148
149
150
151			`fs-syn`
152
153
154			`dest_dir`
155			`../verilog/syn/`
156			`verilogSourcelibraryDir`
157
158
159
160
161
162
163
164
165
166
167
168
169			`sim:Simulation:`
170			`Verilog`
171
172
173			`fs-sim`
174
175
176
177
178			`syn:Synthesis:`
179			`Verilog`
180
181
182			`fs-syn`
183
184
185
186
187			`doc`
188
189
190			`spirit:library="Testbench"`
191			`spirit:name="toolflow"`
192			`spirit:version="documentation"/>`
193
194			`:Documentation:`
195			`Verilog`
196
197
198
199
200
201
202
203			`STOP_WIDTH1`
204			`BAD_WIDTH1`
205
206
207
208
209
210			`START`
211			`wire`
212			`in`
213
214
215			`STOP`
216			`wire`
217			`inSTOP_WIDTH-10`
218
219
220			`BAD`
221			`wire`
222			`inBAD_WIDTH-10`
223
224
225			`FAIL`
226			`reg`
227			`out`
228
229
230
231			`FINISH`
232			`reg`
233			`out`
234
235
236
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