URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [rtl/] [xml/] [clock_gen_def.xml] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
clock_gen
def  default
 
 

 
 
 
 master_clk
  
  
  
    
      
        clk
        clk
wire

      
 
    
 
 
 
 
 
 master_reset
  
  
  
    
      
        reset
        reset
reg

      
    
 
 
 
 

 
 
 

 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      clock_gen_def
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
  
    
      destination
      clock_gen_def
    
  

 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 

       
 
 
             
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
  
 
 STOP_WIDTH1
 BAD_WIDTH1

 
 

 
START
wire
in

 
STOP
wire
inSTOP_WIDTH-10

 
BAD
wire
inBAD_WIDTH-10

 
FAIL
reg
out

 
 
FINISH
reg
out

 

 
 
 
 
 
 

 
 
 
 
 
 
   
      fs-common
 
 
 
 
   
 
 
  
      fs-sim
 
      
        
        ../verilog/clock_gen_sim
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
     
        
        ../verilog/sim/clock_gen_def
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
    
    fs-syn
 
      
        
        ../verilog/clock_gen_syn
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
     
        
        ../verilog/syn/clock_gen_def
        verilogSourcemodule
      
 
 
     
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
  
 
 
 
 
 
 

 
 

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [rtl/] [xml/] [clock_gen_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`clock_gen`
40			`def default`
41
42
43
44
45
46
47			`master_clk`
48
49
50
51
52
53			`clk`
54			`clk`
55	134	jt_eaton	`wire`
56	131	jt_eaton
57
58
59
60
61
62
63
64
65			`master_reset`
66
67
68
69
70
71			`reset`
72			`reset`
73			`reg`
74
75
76
77
78
79
80
81
82
83
84
85	133	jt_eaton
86
87
88
89
90	134	jt_eaton	`gen_verilog_sim`
91			`104.0`
92	133	jt_eaton	`none`
93			`:Simulation:`
94	134	jt_eaton	`./tools/verilog/gen_verilog`
95
96	133	jt_eaton
97	134	jt_eaton	`destination`
98			`clock_gen_def`
99	133	jt_eaton
100
101
102
103
104
105	134	jt_eaton	`gen_verilog_syn`
106			`104.0`
107	133	jt_eaton	`none`
108	134	jt_eaton	`:Synthesis:`
109			`./tools/verilog/gen_verilog`
110
111	133	jt_eaton
112	134	jt_eaton	`destination`
113			`clock_gen_def`
114	133	jt_eaton
115
116
117
118
119	134	jt_eaton
120	133	jt_eaton
121
122
123
124
125
126
127
128
129
130
131
132
133	131	jt_eaton
134
135	134	jt_eaton
136
137	131	jt_eaton
138
139	134	jt_eaton
140			`verilog`
141
142
143			`spirit:library="Testbench"`
144			`spirit:name="toolflow"`
145			`spirit:version="verilog"/>`
146
147
148	131	jt_eaton
149
150
151
152			`sim:Simulation:`
153			`Verilog`
154
155
156			`fs-sim`
157
158
159
160
161			`syn:Synthesis:`
162			`Verilog`
163
164
165			`fs-syn`
166
167
168
169
170			`doc`
171
172
173			`spirit:library="Testbench"`
174			`spirit:name="toolflow"`
175			`spirit:version="documentation"/>`
176
177			`:Documentation:`
178			`Verilog`
179
180
181
182
183
184
185
186			`STOP_WIDTH1`
187			`BAD_WIDTH1`
188
189
190
191
192
193			`START`
194			`wire`
195			`in`
196
197
198			`STOP`
199			`wire`
200			`inSTOP_WIDTH-10`
201
202
203			`BAD`
204			`wire`
205			`inBAD_WIDTH-10`
206
207
208			`FAIL`
209			`reg`
210			`out`
211
212
213
214			`FINISH`
215			`reg`
216			`out`
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231	134	jt_eaton
232	131	jt_eaton
233	134	jt_eaton
234			`fs-common`
235	131	jt_eaton
236
237
238
239	134	jt_eaton
240
241
242
243			`fs-sim`
244
245
246
247			`../verilog/clock_gen_sim`
248			`verilogSourcefragment`
249
250
251
252
253
254			`../verilog/copyright`
255			`verilogSourceinclude`
256
257
258
259
260			`../verilog/sim/clock_gen_def`
261			`verilogSourcemodule`
262
263
264
265
266			`dest_dir`
267			`../views/sim/`
268			`verilogSourcelibraryDir`
269
270
271
272
273
274
275			`fs-syn`
276
277
278
279			`../verilog/clock_gen_syn`
280			`verilogSourcefragment`
281
282
283
284
285
286			`../verilog/copyright`
287			`verilogSourceinclude`
288
289
290
291
292			`../verilog/syn/clock_gen_def`
293			`verilogSourcemodule`
294
295
296
297
298			`dest_dir`
299			`../views/syn/`
300			`verilogSourcelibraryDir`
301
302
303
304
305
306
307
308
309
310
311
312	131	jt_eaton
313
314