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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [display_model/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 133

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reg [3:0] decode;
 
always@(*)
if      (seg == 7'b1000000) decode = 4'b0000;
else if (seg == 7'b1111001) decode = 4'b0001;
else if (seg == 7'b0100100) decode = 4'b0010;
else if (seg == 7'b0110000) decode = 4'b0011;
else if (seg == 7'b0011001) decode = 4'b0100;
else if (seg == 7'b0010010) decode = 4'b0101;
else if (seg == 7'b0000010) decode = 4'b0110;
else if (seg == 7'b1111000) decode = 4'b0111;
else if (seg == 7'b0000000) decode = 4'b1000;
else if (seg == 7'b0011000) decode = 4'b1001;
else if (seg == 7'b0001000) decode = 4'b1010;
else if (seg == 7'b0000011) decode = 4'b1011;
else if (seg == 7'b1000110) decode = 4'b1100;
else if (seg == 7'b0100001) decode = 4'b1101;
else if (seg == 7'b0000110) decode = 4'b1110;
else                        decode = 4'b1111;
 
 
 
 
 
 
reg [3:0] segment0;
reg [3:0] segment1;
reg [3:0] segment2;
reg [3:0] segment3;
 
 
 
always@(posedge clk)
if(reset)             segment0 <= 4'h0;
else
if(!an[0])            segment0 <= decode;
else                  segment0 <= segment0;
 
 
always@(posedge clk)
if(reset)             segment1 <= 4'h0;
else
if(!an[1])            segment1 <= decode;
else                  segment1 <= segment1;
 
 
always@(posedge clk)
if(reset)             segment2 <= 4'h0;
else
if(!an[2])            segment2 <= decode;
else                  segment2 <= segment2;
 
 
always@(posedge clk)
if(reset)             segment3 <= 4'h0;
else
if(!an[3])            segment3 <= decode;
else                  segment3 <= segment3;
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	133	jt_eaton
2
3
4
5
6
7			`reg [3:0] decode;`
8
9			`always@(*)`
10			`if (seg == 7'b1000000) decode = 4'b0000;`
11			`else if (seg == 7'b1111001) decode = 4'b0001;`
12			`else if (seg == 7'b0100100) decode = 4'b0010;`
13			`else if (seg == 7'b0110000) decode = 4'b0011;`
14			`else if (seg == 7'b0011001) decode = 4'b0100;`
15			`else if (seg == 7'b0010010) decode = 4'b0101;`
16			`else if (seg == 7'b0000010) decode = 4'b0110;`
17			`else if (seg == 7'b1111000) decode = 4'b0111;`
18			`else if (seg == 7'b0000000) decode = 4'b1000;`
19			`else if (seg == 7'b0011000) decode = 4'b1001;`
20			`else if (seg == 7'b0001000) decode = 4'b1010;`
21			`else if (seg == 7'b0000011) decode = 4'b1011;`
22			`else if (seg == 7'b1000110) decode = 4'b1100;`
23			`else if (seg == 7'b0100001) decode = 4'b1101;`
24			`else if (seg == 7'b0000110) decode = 4'b1110;`
25			`else decode = 4'b1111;`
26
27
28
29
30
31
32			`reg [3:0] segment0;`
33			`reg [3:0] segment1;`
34			`reg [3:0] segment2;`
35			`reg [3:0] segment3;`
36
37
38
39			`always@(posedge clk)`
40			`if(reset) segment0 <= 4'h0;`
41			`else`
42			`if(!an[0]) segment0 <= decode;`
43			`else segment0 <= segment0;`
44
45
46			`always@(posedge clk)`
47			`if(reset) segment1 <= 4'h0;`
48			`else`
49			`if(!an[1]) segment1 <= decode;`
50			`else segment1 <= segment1;`
51
52
53			`always@(posedge clk)`
54			`if(reset) segment2 <= 4'h0;`
55			`else`
56			`if(!an[2]) segment2 <= decode;`
57			`else segment2 <= segment2;`
58
59
60			`always@(posedge clk)`
61			`if(reset) segment3 <= 4'h0;`
62			`else`
63			`if(!an[3]) segment3 <= decode;`
64			`else segment3 <= segment3;`
65
66
67
68
69
70
71
72

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [display_model/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 133