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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [display_model/] [rtl/] [xml/] [display_model_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
display_model
def  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
 
    
 
 
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
  
 
 
 

       
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
dp
wire
in

 
 
 
 
seg
wire
in60

 
 
an
wire
in30

 
 
 
 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [display_model/] [rtl/] [xml/] [display_model_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	133	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`display_model`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog_sim`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59			`top.out.sim`
60
61
62			`dest_dir`
63			`../verilog`
64
65
66
67
68
69
70			`gen_verilog_syn`
71			`104.0`
72			`none`
73			`:Synthesis:`
74			`./tools/verilog/gen_verilog`
75
76
77			`destination`
78			`top.out.syn`
79
80
81			`dest_dir`
82			`../verilog`
83
84
85
86
87
88
89
90			`gen_verilogLib_sim`
91			`105.0`
92			`none`
93			`:Simulation:`
94			`./tools/verilog/gen_verilogLib`
95
96
97			`dest_dir`
98			`../views`
99
100
101			`view`
102			`sim`
103
104
105
106
107
108			`gen_verilogLib_syn`
109			`105.0`
110			`none`
111			`:Synthesis:`
112			`./tools/verilog/gen_verilogLib`
113
114
115			`dest_dir`
116			`../views`
117
118
119			`view`
120			`syn`
121
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132			`fs-sim`
133
134
135
136			`../verilog/copyright.v`
137			`verilogSourceinclude`
138
139
140
141
142			`../verilog/sim/top.out.sim`
143			`verilogSourcemodule`
144
145
146
147
148
149			`../verilog/top.rtl`
150			`verilogSourcefragment`
151
152
153
154
155
156			`dest_dir../views/sim/`
157			`verilogSourcelibraryDir`
158
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174			`fs-syn`
175
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178			`../verilog/copyright.v`
179			`verilogSourceinclude`
180
181
182
183
184			`../verilog/syn/top.out.syn`
185			`verilogSourcemodule`
186
187
188
189
190
191			`../verilog/top.rtl`
192			`verilogSourcefragment`
193
194
195
196
197
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200			`dest_dir../views/syn/`
201			`verilogSourcelibraryDir`
202
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221			`sim:Simulation:`
222
223			`Verilog`
224
225
226			`fs-sim`
227
228
229
230
231
232			`syn:Synthesis:`
233
234			`Verilog`
235
236
237			`fs-syn`
238
239
240
241
242
243			`doc`
244
245
246			`spirit:library="Testbench"`
247			`spirit:name="toolflow"`
248			`spirit:version="documentation"/>`
249
250			`:Documentation:`
251			`Verilog`
252
253
254
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256
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259
260
261
262			`clk`
263			`wire`
264			`in`
265
266
267			`reset`
268			`wire`
269			`in`
270
271
272
273
274			`dp`
275			`wire`
276			`in`
277
278
279
280
281
282			`seg`
283			`wire`
284			`in60`
285
286
287
288			`an`
289			`wire`
290			`in30`
291
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