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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [display_model/] [rtl/] [xml/] [display_model_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
display_model
def  default
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      display_model_def
    
  

 
 
 

 
 
 

       
 
 
           
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
dp
wire
in

 
 
 
 
seg
wire
in60

 
 
an
wire
in30

 
 
 
 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/display_model_def
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
 
 
    
      fs-syn
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/display_model_def
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [display_model/] [rtl/] [xml/] [display_model_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	133	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`display_model`
40			`def default`
41
42
43
44
45
46	134	jt_eaton	`gen_verilog`
47	133	jt_eaton	`104.0`
48			`none`
49	134	jt_eaton	`common`
50	133	jt_eaton	`./tools/verilog/gen_verilog`
51
52
53			`destination`
54	134	jt_eaton	`display_model_def`
55	133	jt_eaton
56
57
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65	134	jt_eaton
66
67	133	jt_eaton
68
69	134	jt_eaton
70			`verilog`
71
72
73			`spirit:library="Testbench"`
74			`spirit:name="toolflow"`
75			`spirit:version="verilog"/>`
76
77
78	133	jt_eaton
79
80
81	134	jt_eaton
82			`commoncommon`
83			`Verilog`
84
85
86			`fs-common`
87
88
89	133	jt_eaton
90
91
92
93
94			`sim:Simulation:`
95
96			`Verilog`
97
98
99			`fs-sim`
100
101
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103
104
105			`syn:Synthesis:`
106
107			`Verilog`
108
109
110			`fs-syn`
111
112
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114
115
116			`doc`
117
118
119			`spirit:library="Testbench"`
120			`spirit:name="toolflow"`
121			`spirit:version="documentation"/>`
122
123			`:Documentation:`
124			`Verilog`
125
126
127
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129
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132
133
134
135			`clk`
136			`wire`
137			`in`
138
139
140			`reset`
141			`wire`
142			`in`
143
144
145
146
147			`dp`
148			`wire`
149			`in`
150
151
152
153
154
155			`seg`
156			`wire`
157			`in60`
158
159
160
161			`an`
162			`wire`
163			`in30`
164
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185	134	jt_eaton
186	133	jt_eaton
187	134	jt_eaton
188			`fs-common`
189	133	jt_eaton
190	134	jt_eaton
191
192			`../verilog/top.rtl`
193			`verilogSourcefragment`
194
195	133	jt_eaton
196
197	134	jt_eaton
198	133	jt_eaton
199
200
201	134	jt_eaton
202
203
204			`fs-sim`
205
206
207
208			`../verilog/copyright`
209			`verilogSourceinclude`
210
211
212
213
214			`../verilog/common/display_model_def`
215			`verilogSourcemodule`
216
217
218
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220			`dest_dir../views/sim/`
221			`verilogSourcelibraryDir`
222
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233
234
235			`fs-syn`
236
237
238
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240			`../verilog/copyright`
241			`verilogSourceinclude`
242
243
244
245
246			`../verilog/common/display_model_def`
247			`verilogSourcemodule`
248
249
250
251			`dest_dir../views/syn/`
252			`verilogSourcelibraryDir`
253
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274	133	jt_eaton