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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

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reg   [WIDTH-1:0]          filtered_value;
reg   [WIDTH:1]            fail;
 
assign         signal = drive_value;
 
always @(posedge clk)   filtered_value <=   signal;
always @(posedge clk)   fail           <=   mask & (signal^ expected_value);
 
 
initial
  begin
    cg.next(3);
    while(1)
      begin
      if(fail !== {WIDTH{1'b0}})
           begin
           $display("%t %m              value %x   failure on bit(s)  %b",$realtime,filtered_value,fail );
           cg.fail(MESG);
           end
      cg.next(1);
      end // while (1)
  end // initial begin
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`reg [WIDTH-1:0] filtered_value;`
3			`reg [WIDTH:1] fail;`
4
5			`assign signal = drive_value;`
6
7			`always @(posedge clk) filtered_value <= signal;`
8			`always @(posedge clk) fail <= mask & (signal^ expected_value);`
9
10
11			`initial`
12			`begin`
13			`cg.next(3);`
14			`while(1)`
15			`begin`
16			`if(fail !== {WIDTH{1'b0}})`
17			`begin`
18			`$display("%t %m value %x failure on bit(s) %b",$realtime,filtered_value,fail );`
19			`cg.fail(MESG);`
20			`end`
21			`cg.next(1);`
22			`end // while (1)`
23			`end // initial begin`
24
25
26
27
28

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [verilog/] [top.body] - Blame information for rev 131