Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

Testbench

io_probe

def

  gen_verilog_sim

  104.0

  none

  :*Simulation:*

  tools/verilog/gen_verilog

      destination

      io_probe_def

  gen_verilog_syn

  104.0

  none

  :*Synthesis:*

  tools/verilog/gen_verilog

      destination

      io_probe_def

                                verilog

                                verilog

                                io_probe_def

                                                WIDTH

                                                1

                                        fs-sim

                                rtl

                                verilog:Kactus2:

                                verilog

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

MESG" "

WIDTH1

RESET{WIDTH{1'bz}}

IN_DELAY5

OUT_DELAY15

OUT_WIDTH10

clk

wire

in

drive_value

wire

in

WIDTH-10

expected_value

wire

in

WIDTH-10

mask

wire

in

WIDTH-10

signal

wire

inout

WIDTH-10

      fs-sim

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/sim/io_probe_def

        verilogSourcemodule

        ../verilog/top.body

        verilogSourcefragment

        dest_dir../views/sim/

        verilogSourcelibraryDir

      fs-syn

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/syn/io_probe_def

        verilogSourcemodule

        dest_dir../views/syn/

        verilogSourcelibraryDir