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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
io_probe
def  default
 
 
 
 
 
 
 

 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 
 
 

       
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

MESG" "
WIDTH1
RESET{WIDTH{1'bz}}
IN_DELAY5
OUT_DELAY15
OUT_WIDTH10

 

 
clk
wire
in

 
 
drive_value
wire
in
WIDTH-10

 
 
expected_value
wire
in
WIDTH-10

 
mask
wire
in
WIDTH-10

 
 
signal
wire
inout
WIDTH-10

 
 
 
 

 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`io_probe`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51	133	jt_eaton	`elab_verilog`
52			`103.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/elab_verilog`
56
57
58			`dest_dir`
59			`io_ports`
60
61
62
63
64
65
66
67
68
69	131	jt_eaton	`gen_verilog_sim`
70			`104.0`
71			`none`
72			`:Simulation:`
73			`./tools/verilog/gen_verilog`
74
75
76			`destination`
77			`top.out.sim`
78
79
80			`dest_dir`
81			`../verilog`
82
83
84
85
86
87
88			`gen_verilog_syn`
89			`104.0`
90			`none`
91			`:Synthesis:`
92			`./tools/verilog/gen_verilog`
93
94
95			`destination`
96			`top.out.syn`
97
98
99			`dest_dir`
100			`../verilog`
101
102
103
104
105
106
107
108			`gen_verilogLib_sim`
109			`105.0`
110			`none`
111			`:Simulation:`
112			`./tools/verilog/gen_verilogLib`
113
114
115			`dest_dir`
116			`../views`
117
118
119			`view`
120			`sim`
121
122
123
124
125
126
127
128			`gen_verilogLib_syn`
129			`105.0`
130			`none`
131			`:Synthesis:`
132			`./tools/verilog/gen_verilogLib`
133
134
135			`dest_dir`
136			`../views`
137
138
139			`view`
140			`syn`
141
142
143
144
145
146
147
148
149
150
151
152			`fs-sim`
153
154
155
156			`../verilog/copyright.v`
157			`verilogSourceinclude`
158
159
160
161
162			`../verilog/sim/top.out.sim`
163			`verilogSourcemodule`
164
165
166
167
168
169			`../verilog/top.body`
170			`verilogSourcefragment`
171
172
173
174			`dest_dir../views/sim/`
175			`verilogSourcelibraryDir`
176
177
178
179
180
181
182
183
184
185
186			`fs-syn`
187
188
189
190			`../verilog/copyright.v`
191			`verilogSourceinclude`
192
193
194
195
196			`../verilog/syn/top.out.syn`
197			`verilogSourcemodule`
198
199
200
201			`dest_dir../views/syn/`
202			`verilogSourcelibraryDir`
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229			`sim:Simulation:`
230
231			`Verilog`
232
233
234			`fs-sim`
235
236
237
238
239			`syn:Synthesis:`
240
241			`Verilog`
242
243
244			`fs-syn`
245
246
247
248
249
250			`doc`
251
252
253			`spirit:library="Testbench"`
254			`spirit:name="toolflow"`
255			`spirit:version="documentation"/>`
256
257			`:Documentation:`
258			`Verilog`
259
260
261
262
263
264
265
266			`MESG" "`
267			`WIDTH1`
268			`RESET{WIDTH{1'bz}}`
269			`IN_DELAY5`
270			`OUT_DELAY15`
271			`OUT_WIDTH10`
272
273
274
275
276			`clk`
277			`wire`
278			`in`
279
280
281
282			`drive_value`
283			`wire`
284			`in`
285			`WIDTH-10`
286
287
288
289			`expected_value`
290			`wire`
291			`in`
292			`WIDTH-10`
293
294
295			`mask`
296			`wire`
297			`in`
298			`WIDTH-10`
299
300
301
302			`signal`
303			`wire`
304			`inout`
305			`WIDTH-10`
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323