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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
io_probe
def  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      io_probe_def
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      io_probe_def
    
  

 
 
 

 
 
 
 
 
 
 
 

       
 
 
 
            
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

MESG" "
WIDTH1
RESET{WIDTH{1'bz}}
IN_DELAY5
OUT_DELAY15
OUT_WIDTH10

 

 
clk
wire
in

 
 
drive_value
wire
in
WIDTH-10

 
 
expected_value
wire
in
WIDTH-10

 
mask
wire
in
WIDTH-10

 
 
signal
wire
inout
WIDTH-10

 
 
 
 

 

 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/io_probe_def
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/io_probe_def
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`io_probe`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog_sim`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59	134	jt_eaton	`io_probe_def`
60	131	jt_eaton
61
62
63
64
65
66			`gen_verilog_syn`
67			`104.0`
68			`none`
69			`:Synthesis:`
70			`./tools/verilog/gen_verilog`
71
72
73			`destination`
74	134	jt_eaton	`io_probe_def`
75	131	jt_eaton
76
77
78
79
80
81
82
83
84
85
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88
89
90	134	jt_eaton
91
92	131	jt_eaton
93
94
95	134	jt_eaton
96			`verilog`
97
98
99			`spirit:library="Testbench"`
100			`spirit:name="toolflow"`
101			`spirit:version="verilog"/>`
102
103
104	131	jt_eaton
105
106
107
108
109
110			`sim:Simulation:`
111
112			`Verilog`
113
114
115			`fs-sim`
116
117
118
119
120			`syn:Synthesis:`
121
122			`Verilog`
123
124
125			`fs-syn`
126
127
128
129
130
131			`doc`
132
133
134			`spirit:library="Testbench"`
135			`spirit:name="toolflow"`
136			`spirit:version="documentation"/>`
137
138			`:Documentation:`
139			`Verilog`
140
141
142
143
144
145
146
147			`MESG" "`
148			`WIDTH1`
149			`RESET{WIDTH{1'bz}}`
150			`IN_DELAY5`
151			`OUT_DELAY15`
152			`OUT_WIDTH10`
153
154
155
156
157			`clk`
158			`wire`
159			`in`
160
161
162
163			`drive_value`
164			`wire`
165			`in`
166			`WIDTH-10`
167
168
169
170			`expected_value`
171			`wire`
172			`in`
173			`WIDTH-10`
174
175
176			`mask`
177			`wire`
178			`in`
179			`WIDTH-10`
180
181
182
183			`signal`
184			`wire`
185			`inout`
186			`WIDTH-10`
187
188
189
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195
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197
198
199	134	jt_eaton
200	131	jt_eaton
201	134	jt_eaton
202			`fs-sim`
203	131	jt_eaton
204	134	jt_eaton
205
206			`../verilog/copyright`
207			`verilogSourceinclude`
208
209	131	jt_eaton
210	134	jt_eaton
211
212			`../verilog/sim/io_probe_def`
213			`verilogSourcemodule`
214
215	131	jt_eaton
216
217	134	jt_eaton
218
219			`../verilog/top.body`
220			`verilogSourcefragment`
221
222
223
224			`dest_dir../views/sim/`
225			`verilogSourcelibraryDir`
226
227
228
229
230
231
232
233
234
235
236			`fs-syn`
237
238
239
240			`../verilog/copyright`
241			`verilogSourceinclude`
242
243
244
245
246			`../verilog/syn/io_probe_def`
247			`verilogSourcemodule`
248
249
250
251			`dest_dir../views/syn/`
252			`verilogSourcelibraryDir`
253
254
255
256
257
258
259
260
261
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264
265
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273	131	jt_eaton