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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
io_probe
in  default
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      io_probe_in
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      io_probe_in
    
  

 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
 
 
 
 

       
 
 
          
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

MESG" "
WIDTH1
IN_DELAY5

 

 
clk
wire
in

 
 
expected_value
wire
in
WIDTH-10

 
mask
wire
in
WIDTH-10

 
 
signal
wire
in
WIDTH-10

 
 
 
 

 

 
 
 
 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/io_probe_in
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.body.in
        verilogSourcefragment
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/io_probe_in
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	134	jt_eaton
2	131	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`io_probe`
40			`in default`
41
42
43
44
45			`gen_verilog_sim`
46			`104.0`
47			`none`
48			`:Simulation:`
49			`./tools/verilog/gen_verilog`
50
51
52			`destination`
53	134	jt_eaton	`io_probe_in`
54	131	jt_eaton
55
56
57
58
59			`gen_verilog_syn`
60			`104.0`
61			`none`
62			`:Synthesis:`
63			`./tools/verilog/gen_verilog`
64
65
66			`destination`
67	134	jt_eaton	`io_probe_in`
68	131	jt_eaton
69
70
71
72
73
74			`gen_verilogLib_sim`
75			`105.0`
76			`none`
77			`:Simulation:`
78			`./tools/verilog/gen_verilogLib`
79
80
81			`dest_dir`
82			`../views`
83
84
85			`view`
86			`sim`
87
88
89
90
91
92
93			`gen_verilogLib_syn`
94			`105.0`
95			`none`
96			`:Synthesis:`
97			`./tools/verilog/gen_verilogLib`
98
99
100			`dest_dir`
101			`../views`
102
103
104			`view`
105			`syn`
106
107
108
109
110
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112
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116
117
118	134	jt_eaton
119
120	131	jt_eaton
121
122	134	jt_eaton
123			`verilog`
124
125
126			`spirit:library="Testbench"`
127			`spirit:name="toolflow"`
128			`spirit:version="verilog"/>`
129
130
131	131	jt_eaton
132
133
134
135
136
137
138			`sim:Simulation:`
139
140			`Verilog`
141
142
143			`fs-sim`
144
145
146
147
148			`syn:Synthesis:`
149
150			`Verilog`
151
152
153			`fs-syn`
154
155
156
157
158
159			`doc`
160
161
162			`spirit:library="Testbench"`
163			`spirit:name="toolflow"`
164			`spirit:version="documentation"/>`
165
166			`:Documentation:`
167			`Verilog`
168
169
170
171
172
173
174
175			`MESG" "`
176			`WIDTH1`
177			`IN_DELAY5`
178
179
180
181
182			`clk`
183			`wire`
184			`in`
185
186
187
188			`expected_value`
189			`wire`
190			`in`
191			`WIDTH-10`
192
193
194			`mask`
195			`wire`
196			`in`
197			`WIDTH-10`
198
199
200
201			`signal`
202			`wire`
203			`in`
204			`WIDTH-10`
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220	134	jt_eaton
221	131	jt_eaton
222	134	jt_eaton
223			`fs-sim`
224	131	jt_eaton
225	134	jt_eaton
226
227			`../verilog/copyright`
228			`verilogSourceinclude`
229
230
231
232
233			`../verilog/sim/io_probe_in`
234			`verilogSourcemodule`
235
236
237
238
239
240			`../verilog/top.body.in`
241			`verilogSourcefragment`
242
243
244
245			`dest_dir../views/sim/`
246			`verilogSourcelibraryDir`
247
248
249
250
251
252
253
254
255
256
257			`fs-syn`
258
259
260
261			`../verilog/copyright`
262			`verilogSourceinclude`
263
264
265
266
267			`../verilog/syn/io_probe_in`
268			`verilogSourcemodule`
269
270
271
272			`dest_dir../views/syn/`
273			`verilogSourcelibraryDir`
274
275
276
277
278
279
280
281
282
283
284
285
286
287
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290
291
292	131	jt_eaton