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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [jtag_model/] [rtl/] [verilog/] [jtag_model_def.v] - Blame information for rev 131

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1 131 jt_eaton 
/**********************************************************************/
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/*                                                                    */
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/*             -------                                                */
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/*            /   SOC  \                                              */
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/*           /    GEN   \                                             */
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/*          /     SIM    \                                            */
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/*          ==============                                            */
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/*          |            |                                            */
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/*          |____________|                                            */
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/*                                                                    */
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/*  JTAG Hoset model for  simulations                                 */
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/*                                                                    */
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/*                                                                    */
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/*  Author(s):                                                        */
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/*      - John Eaton, jt_eaton@opencores.org                          */
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/*                                                                    */
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/**********************************************************************/
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/*                                                                    */
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/*    Copyright (C) <2010>  <Ouabache Design Works>                   */
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/*                                                                    */
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/*  This source file may be used and distributed without              */
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/*  restriction provided that this copyright statement is not         */
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/*  removed from the file and that any derivative work contains       */
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/*  the original copyright notice and the associated disclaimer.      */
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/*                                                                    */
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/*  This source file is free software; you can redistribute it        */
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/*  and/or modify it under the terms of the GNU Lesser General        */
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/*  Public License as published by the Free Software Foundation;      */
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/*  either version 2.1 of the License, or (at your option) any        */
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/*  later version.                                                    */
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/*                                                                    */
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/*  This source is distributed in the hope that it will be            */
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/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
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/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
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/*  PURPOSE.  See the GNU Lesser General Public License for more      */
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/*  details.                                                          */
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/*                                                                    */
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/*  You should have received a copy of the GNU Lesser General         */
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/*  Public License along with this source; if not, download it        */
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/*  from http://www.opencores.org/lgpl.shtml                          */
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/*                                                                    */
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/**********************************************************************/
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 module
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  jtag_model_def
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    #( parameter
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      DIVCNT=4'h1,
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      SIZE=4)
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     (
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 input   wire                 clk,
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 input   wire                 reset,
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 input   wire                 tdi,
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 output   reg                 tclk,
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 output   reg                 tdo,
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 output   reg                 tms,
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 output   reg                 trst_n);
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reg         tclk_enable;
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reg [SIZE-1:0]   tclk_counter;
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wire        next_tclk_edge;
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wire        next_tclk_pos_edge;
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wire        next_tclk_neg_edge;
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assign next_tclk_edge = (tclk_counter == 4'h0);
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assign next_tclk_pos_edge = next_tclk_edge && (!tclk) ;
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assign next_tclk_neg_edge = next_tclk_edge && ( tclk) ;
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always@(posedge clk)
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  if(reset)         tclk_counter   <= DIVCNT;
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  else
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  if(|tclk_counter) tclk_counter   <= tclk_counter-4'h1;
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  else              tclk_counter   <= DIVCNT;
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always@(posedge clk)
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  if(reset)                 tclk   <= 1'b0;
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  else
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  if(!tclk_enable)          tclk   <= tclk;
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  else
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  if( next_tclk_pos_edge )  tclk   <= 1'b1;
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  else
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  if( next_tclk_neg_edge )  tclk   <= 1'b0;
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  else                      tclk   <= tclk;
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reg actual;
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initial
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    begin
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    tclk_enable          <= 1'b0;
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    tclk                 <= 1'b0;
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    tdo                  <= 1'b1;
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    tms                  <= 1'b1;
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    trst_n               <= 1'b0;
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    end
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task automatic next;
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  input [31:0] num;
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  repeat (num)       @ (posedge clk);
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endtask
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task enable_tclk;
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begin
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    tclk_enable  <= 1'b1;
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end
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endtask
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task enable_trst_n;
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begin
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Clk_bit(1,1,actual);
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Clk_bit(1,1,actual);
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Clk_bit(1,1,actual);
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Clk_bit(1,1,actual);
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Clk_bit(1,1,actual);
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    trst_n   <= 1'b1;
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Clk_bit(1,1,actual);
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end
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endtask
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task enable_reset;
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begin
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Clk_bit(1,0,actual);
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Clk_bit(1,0,actual);
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Clk_bit(1,0,actual);
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Clk_bit(1,0,actual);
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Clk_bit(1,0,actual);
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Clk_bit(1,0,actual);
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Clk_bit(1,0,actual);
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Clk_bit(1,0,actual);
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end
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endtask
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task init;
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begin
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Clk_bit(0,0,actual);
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Clk_bit(0,0,actual);
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Clk_bit(0,0,actual);
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Clk_bit(0,0,actual);
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Clk_bit(0,0,actual);
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Clk_bit(0,0,actual);
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Clk_bit(0,0,actual);
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Clk_bit(0,0,actual);
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end
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endtask
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task Clk_bit;
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   input         TMS;
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   input         TDO;
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   output        ACT;
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   begin
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   while (next_tclk_neg_edge  != 1)
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   begin
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   next(1);
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   end
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   if(TMS)    tms <= 1'b1;
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   else       tms <= 1'b0;
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   if     ( TDO == 1  ) tdo <= 1'b1;
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   else if( TDO == 0  ) tdo <= 1'b0;
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   else                 tdo <= 1'bx;
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   while (next_tclk_pos_edge  != 1)
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   begin
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   next(1);
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   end
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   ACT = tdi;
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  end
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endtask
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/******************************************************************************/
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/* LoadTapInst (<Inst>);                                                      */
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/******************************************************************************/
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task LoadTapInst;   // Load a Tap Instruction that uses the Boundary Register
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  parameter [15:0] JTAG_INST_LENGTH =  4;
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  input [JTAG_INST_LENGTH:1] Inst; // This task starts & ends with the Tap in the RT_IDLE state
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  input [JTAG_INST_LENGTH:1] Inst_Return; //
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  integer i;
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  reg   [JTAG_INST_LENGTH:1]  Ack;
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  begin
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   Clk_bit(1'b1,1'b0,actual); // Transition from RT_IDLE to SELECT_DR
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   Clk_bit(1'b1,1'b0,actual); // Transition from SELECT_DR to SELECT_IR
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   Clk_bit(1'b0,1'b0,actual); // Transition from SELECT_IR to CAPTURE_IR
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   Clk_bit(1'b0,1'b0,actual); // Transition from CAPTURE_IR to SHIFT_IR
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   for (i = 1; i <=  JTAG_INST_LENGTH; i = i+1)  // Shift in Inst
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     begin
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       Clk_bit(( i == JTAG_INST_LENGTH),Inst[i],Ack[i]);
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     end
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   $display  ("%t  %m  LoadTapInst  %b  Expected %b  Received %b  " ,$realtime,Inst,  Inst_Return,  Ack   );
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   if (Ack !== Inst_Return)
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   begin
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   cg.fail  (" LoadTapInst receive error  ");
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   end
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   Clk_bit(1'b1,1'b0,actual); // Transition from EXIT1_IR to UPDATE_IR
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   Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE_IR to RT_IDLE
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  end
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endtask // LoadTapInst
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//***************************************************************************/
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//* Shift Register
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//***************************************************************************/
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task automatic  Shift_Register;    // Initialize boundary register with outputs disabled
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                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
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  parameter [15:0] LENGTH =  100;
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  input           length;
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  input [LENGTH:1]  Dataout;
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  integer length;
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  integer i;
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  reg [LENGTH:1]  DataBack;
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  begin
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    Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
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    Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
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    Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
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    for (i = 1; i <= length; i = i+1)
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       Clk_bit((i==length),Dataout[i],DataBack[i]);
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    $display  ("%t  %m    Shift_data  -%d  wr-%h  rd-%h    ",$realtime,length,Dataout[LENGTH:1],DataBack[LENGTH:1]);
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    Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
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    Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
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  end
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endtask // ShiftRegister
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task automatic  Shift_Cmp_32;    // Initialize boundary register with outputs disabled
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                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
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  parameter [15:0] LENGTH =  32;
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  input [LENGTH:1]  Dataout;
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  input [LENGTH:1]  DataExp;
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  integer i;
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  reg [LENGTH:1]  DataBack;
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  begin
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    Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
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    Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
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    Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
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    for (i = 1; i <= LENGTH; i = i+1)
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       Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
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    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
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   if (DataBack  !== DataExp )
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   begin
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   cg.fail  (" Shift_cmp  receive error  ");
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   end
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    Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
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    Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
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  end
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endtask // ShiftRegister
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  endmodule

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