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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus16_model/] [rtl/] [verilog/] [logic] - Blame information for rev 134

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always@(posedge clk)
  if(reset)
    begin
      addr          <=  24'h0000;
      wdata         <=  16'h0000;
      wr            <=  1'b0;
      rd            <=  1'b0;
      cs            <=  2'b00;
      ub            <=  1'b0;
      lb            <=  1'b0;
      exp_rdata     <=  16'h0000;
      mask_rdata    <=  16'h0000;
   end
 

Line No.	Rev	Author	Line
1	134	jt_eaton	`always@(posedge clk)`
2			`if(reset)`
3			`begin`
4			`addr <= 24'h0000;`
5			`wdata <= 16'h0000;`
6			`wr <= 1'b0;`
7			`rd <= 1'b0;`
8			`cs <= 2'b00;`
9			`ub <= 1'b0;`
10			`lb <= 1'b0;`
11			`exp_rdata <= 16'h0000;`
12			`mask_rdata <= 16'h0000;`
13			`end`
14

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus16_model/] [rtl/] [verilog/] [logic] - Blame information for rev 134