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/**********************************************************************/
/*                                                                    */
/*             -------                                                */
/*            /   SOC  \                                              */
/*           /    GEN   \                                             */
/*          /     SIM    \                                            */
/*          ==============                                            */
/*          |            |                                            */
/*          |____________|                                            */
/*                                                                    */
/*  Microprocessor bus functional model (BFM) for simulations         */
/*                                                                    */
/*                                                                    */
/*  Author(s):                                                        */
/*      - John Eaton, jt_eaton@opencores.org                          */
/*                                                                    */
/**********************************************************************/
/*                                                                    */
/*    Copyright (C) <2010>  <Ouabache Design Works>                   */
/*                                                                    */
/*  This source file may be used and distributed without              */
/*  restriction provided that this copyright statement is not         */
/*  removed from the file and that any derivative work contains       */
/*  the original copyright notice and the associated disclaimer.      */
/*                                                                    */
/*  This source file is free software; you can redistribute it        */
/*  and/or modify it under the terms of the GNU Lesser General        */
/*  Public License as published by the Free Software Foundation;      */
/*  either version 2.1 of the License, or (at your option) any        */
/*  later version.                                                    */
/*                                                                    */
/*  This source is distributed in the hope that it will be            */
/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
/*  PURPOSE.  See the GNU Lesser General Public License for more      */
/*  details.                                                          */
/*                                                                    */
/*  You should have received a copy of the GNU Lesser General         */
/*  Public License along with this source; if not, download it        */
/*  from http://www.opencores.org/lgpl.shtml                          */
/*                                                                    */
/**********************************************************************/
 
 
 
 
 
 
module micro_bus16_model_def
#(parameter OUT_DELAY    = 15,
  parameter OUT_WIDTH    = 10
  )
 
 
 (
  input wire                  clk,
  input wire                  reset,
 
  output reg [23:0]           addr,
  output reg [15:0]           wdata,
  output reg [1:0]            cs,
  output reg                  rd,
  output reg                  wr,
  output reg                  ub,
  output reg                  lb,
 
 
  inout  wire [15:0]           rdata
);
 
 
   reg [15:0]  exp_rdata;
   reg [15:0]  mask_rdata;
 
always@(posedge clk)
  if(reset)
    begin
      addr  <= 24'h0000;
      wdata <=  16'h0000;
      wr    <=  1'b0;
      rd    <=  1'b0;
      cs    <=  2'b00;
      ub    <=  1'b0;
      lb    <=  1'b0;
      exp_rdata    <=  16'h0000;
      mask_rdata    <=  16'h0000;
   end
 
 
 
io_probe_def
 #(.MESG         ("micro rdata Error"),
   .WIDTH        (16),
   .RESET        ({16{1'bz}}),
   .OUT_DELAY    (OUT_DELAY),
   .OUT_WIDTH    (OUT_WIDTH)
  )
rdata_tpb
  (
  .clk            (  clk        ),
  .drive_value    (16'bzzzzzzzzzzzzzzzz  ),
  .expected_value (  exp_rdata  ),
  .mask           (  mask_rdata ),
  .signal         (  rdata      )
  );
 
 
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* ------- */`
4			`/* / SOC \ */`
5			`/* / GEN \ */`
6			`/* / SIM \ */`
7			`/* ============== */`
8			`/* \| \| */`
9			`/* \|____________\| */`
10			`/* */`
11			`/* Microprocessor bus functional model (BFM) for simulations */`
12			`/* */`
13			`/* */`
14			`/* Author(s): */`
15			`/* - John Eaton, jt_eaton@opencores.org */`
16			`/* */`
17			`/**********************************************************************/`
18			`/* */`
19			`/* Copyright (C) <2010> <Ouabache Design Works> */`
20			`/* */`
21			`/* This source file may be used and distributed without */`
22			`/* restriction provided that this copyright statement is not */`
23			`/* removed from the file and that any derivative work contains */`
24			`/* the original copyright notice and the associated disclaimer. */`
25			`/* */`
26			`/* This source file is free software; you can redistribute it */`
27			`/* and/or modify it under the terms of the GNU Lesser General */`
28			`/* Public License as published by the Free Software Foundation; */`
29			`/* either version 2.1 of the License, or (at your option) any */`
30			`/* later version. */`
31			`/* */`
32			`/* This source is distributed in the hope that it will be */`
33			`/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
34			`/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
35			`/* PURPOSE. See the GNU Lesser General Public License for more */`
36			`/* details. */`
37			`/* */`
38			`/* You should have received a copy of the GNU Lesser General */`
39			`/* Public License along with this source; if not, download it */`
40			`/* from http://www.opencores.org/lgpl.shtml */`
41			`/* */`
42			`/**********************************************************************/`
43
44
45
46
47
48
49			`module micro_bus16_model_def`
50			`#(parameter OUT_DELAY = 15,`
51			`parameter OUT_WIDTH = 10`
52			`)`
53
54
55			`(`
56			`input wire clk,`
57			`input wire reset,`
58
59			`output reg [23:0] addr,`
60			`output reg [15:0] wdata,`
61			`output reg [1:0] cs,`
62			`output reg rd,`
63			`output reg wr,`
64			`output reg ub,`
65			`output reg lb,`
66
67
68			`inout wire [15:0] rdata`
69			`);`
70
71
72			`reg [15:0] exp_rdata;`
73			`reg [15:0] mask_rdata;`
74
75			`always@(posedge clk)`
76			`if(reset)`
77			`begin`
78			`addr <= 24'h0000;`
79			`wdata <= 16'h0000;`
80			`wr <= 1'b0;`
81			`rd <= 1'b0;`
82			`cs <= 2'b00;`
83			`ub <= 1'b0;`
84			`lb <= 1'b0;`
85			`exp_rdata <= 16'h0000;`
86			`mask_rdata <= 16'h0000;`
87			`end`
88
89
90
91			`io_probe_def`
92			`#(.MESG ("micro rdata Error"),`
93			`.WIDTH (16),`
94			`.RESET ({16{1'bz}}),`
95			`.OUT_DELAY (OUT_DELAY),`
96			`.OUT_WIDTH (OUT_WIDTH)`
97			`)`
98			`rdata_tpb`
99			`(`
100			`.clk ( clk ),`
101			`.drive_value (16'bzzzzzzzzzzzzzzzz ),`
102			`.expected_value ( exp_rdata ),`
103			`.mask ( mask_rdata ),`
104			`.signal ( rdata )`
105			`);`
106
107
108
109
110
111
112
113			`endmodule`
114

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus16_model/] [rtl/] [verilog/] [top.syn] - Blame information for rev 131