URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus16_model/] [rtl/] [xml/] [micro_bus16_model_def.xml] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
micro_bus16_model
def  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      micro_bus16_model_def
    
  

 
 

  gen_verilog_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      micro_bus16_model_def
    
  

 
 

 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="micro_bus16_model"
                                   spirit:version="def.design"/>
              
 
 
 
           
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

DELAY15
WIDTH16

 

 
clk
wire
in

 
reset
wire
in

 
addr
reg
out
230

 
wdata
reg
out
150

 
rd
reg
out

 
wr
reg
out

 
lb
reg
out

 
 
ub
reg
out

 
rdata
wire
in
150

 
 
cs
reg
out
10

 
 
 

 

 
 
 
 
  
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/logic
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tasks
        verilogSourcefragment
      
 
      
        
        ../verilog/sim/micro_bus16_model_def
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/logic
        verilogSourcefragment
      
 
 
      
        
        ../verilog/syn/micro_bus16_model_def
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
  
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus16_model/] [rtl/] [xml/] [micro_bus16_model_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`micro_bus16_model`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51	134	jt_eaton	`gen_verilog_sim`
52	131	jt_eaton	`105.0`
53			`none`
54			`:Simulation:`
55	134	jt_eaton	`./tools/verilog/gen_verilog`
56	131	jt_eaton
57
58	134	jt_eaton	`destination`
59			`micro_bus16_model_def`
60	131	jt_eaton
61
62
63
64
65
66	134	jt_eaton	`gen_verilog_syn`
67	131	jt_eaton	`105.0`
68			`none`
69			`:Synthesis:`
70	134	jt_eaton	`./tools/verilog/gen_verilog`
71	131	jt_eaton
72
73	134	jt_eaton	`destination`
74			`micro_bus16_model_def`
75	131	jt_eaton
76
77
78
79
80
81
82
83
84
85
86
87
88
89			`Hierarchical`
90
91
92			`spirit:library="Testbench"`
93	134	jt_eaton	`spirit:name="micro_bus16_model"`
94	131	jt_eaton	`spirit:version="def.design"/>`
95
96
97
98
99	134	jt_eaton
100			`verilog`
101
102
103			`spirit:library="Testbench"`
104			`spirit:name="toolflow"`
105			`spirit:version="verilog"/>`
106
107
108
109
110
111
112	131	jt_eaton
113			`sim:Simulation:`
114
115			`Verilog`
116
117
118			`fs-sim`
119
120
121
122
123			`syn:Synthesis:`
124
125			`Verilog`
126
127
128			`fs-syn`
129
130
131
132
133
134			`doc`
135
136
137			`spirit:library="Testbench"`
138			`spirit:name="toolflow"`
139			`spirit:version="documentation"/>`
140
141			`:Documentation:`
142			`Verilog`
143
144
145
146
147
148
149
150
151
152
153	134	jt_eaton	`DELAY15`
154			`WIDTH16`
155	131	jt_eaton
156
157
158
159			`clk`
160			`wire`
161			`in`
162
163
164			`reset`
165			`wire`
166			`in`
167
168
169			`addr`
170			`reg`
171			`out`
172			`230`
173
174
175			`wdata`
176			`reg`
177			`out`
178			`150`
179
180
181			`rd`
182			`reg`
183			`out`
184
185
186			`wr`
187			`reg`
188			`out`
189
190
191			`lb`
192			`reg`
193			`out`
194
195
196
197			`ub`
198			`reg`
199			`out`
200
201
202			`rdata`
203			`wire`
204	134	jt_eaton	`in`
205	131	jt_eaton	`150`
206
207
208	134	jt_eaton
209			`cs`
210			`reg`
211			`out`
212			`10`
213
214
215
216
217	131	jt_eaton
218
219
220
221
222	134	jt_eaton
223
224
225
226			`fs-sim`
227
228
229
230			`../verilog/copyright`
231			`verilogSourceinclude`
232
233
234
235
236
237			`../verilog/logic`
238			`verilogSourcefragment`
239
240
241
242
243
244			`../verilog/tasks`
245			`verilogSourcefragment`
246
247
248
249
250			`../verilog/sim/micro_bus16_model_def`
251			`verilogSourcemodule`
252
253
254
255
256			`dest_dir../views/sim/`
257			`verilogSourcelibraryDir`
258
259
260
261
262
263
264
265
266			`fs-syn`
267
268
269
270			`../verilog/copyright`
271			`verilogSourceinclude`
272
273
274
275
276
277			`../verilog/logic`
278			`verilogSourcefragment`
279
280
281
282
283
284			`../verilog/syn/micro_bus16_model_def`
285			`verilogSourcemodule`
286
287
288
289			`dest_dir../views/syn/`
290			`verilogSourcelibraryDir`
291
292
293
294
295
296
297
298
299
300	131	jt_eaton