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module micro_bus_model_def

#(parameter addr_width   = 16,

  parameter OUT_DELAY    = 15,

  parameter OUT_WIDTH    = 10

  )

 (

  input wire                  clk,

  input wire                  reset,

  output reg [addr_width-1:0]           addr,

  output reg [7:0]            wdata,

  output reg                  rd,

  output reg                  wr,

  output reg                  cs,

  inout  wire [7:0]           rdata

);

   reg [7:0]  exp_rdata;

   reg [7:0]  mask_rdata;

always@(posedge clk)

  if(reset)

    begin

      addr  <= 16'h0000;

      wdata <=  8'h00;

      wr    <=  1'b0;

      rd    <=  1'b0;

      cs    <=  1'b1;

      exp_rdata    <=  8'h00;

      mask_rdata    <=  8'h00;

   end

io_probe_in

 #(.MESG         ("micro rdata Error"),

   .WIDTH        (8)

  )

rdata_tpb

  (

  .clk            (  clk        ),

  .expected_value (  exp_rdata  ),

  .mask           (  mask_rdata ),

  .signal         (  rdata      )

  );

  // Tasks

task automatic next;

  input [31:0] num;

  repeat (num)       @ (posedge clk);

endtask // next

  // write cycle

  task u_write;

    input [addr_width-1:0] a;

    input  [7:0] d;

    begin

      $display("%t %m cycle %x %x",$realtime,a,d );

      addr  <= a;

      wdata <= d;

      rd    <= 1'b0;

      wr    <= 1'b1;

      next(1);

      wr     <= 1'b0;

      next(1);

    end

  endtask

  // read cycle

  task u_read;

    input   [addr_width-1:0]  a;

    output  [7:0]   d;

     begin

      addr  <= a;

      wdata <= 8'h00;

      rd    <= 1'b1;

      wr    <= 1'b0;

      next(2);

      d     <= rdata;

      $display("%t %m  cycle %x %x",$realtime,a,rdata );

      rd    <= 1'b1;

      next(1);

      rd    <= 1'b0;

    end

  endtask

  // Compare cycle (read data from location and compare with expected data)

  task u_cmp;

    input  [addr_width-1:0] a;

    input  [7:0] d_exp;

     begin

      addr      <= a;

      wdata     <= 8'h00;

      rd        <= 1'b1;

      wr        <= 1'b0;

      exp_rdata <= d_exp;

      next(1);

      mask_rdata  <= 8'hff;

      next(1);

      $display("%t %m   cycle %x %x",$realtime,a,d_exp );

      mask_rdata <= 8'h00;

      rd         <= 1'b0;

   end

  endtask

endmodule