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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus_model/] [rtl/] [verilog/] [top.syn] - Blame information for rev 133

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Line No. Rev Author Line
1 131 jt_eaton
 
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always@(posedge clk)
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  if(reset)
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    begin
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      addr          <= 16'h0000;
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      wdata         <=  8'h00;
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      wr            <=  1'b0;
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      rd            <=  1'b0;
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      cs            <=  1'b1;
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      exp_rdata     <=  8'h00;
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      mask_rdata    <=  8'h00;
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   end
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