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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus_model/] [rtl/] [xml/] [micro_bus_model_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
micro_bus_model
def  default
 
 
 
 

 
 
mb
  
  
  
    
 
 
      
        addr
        
        addr
          addr_width-10
        
      
 
      
        wdata
        
        wdata
          70
        
      
 
      
        rd
        
        rd
        
      
 
 
      
        wr
        
        wr
        
      
 
 
      
        cs
        
        cs
        
      
 
 
 
    
 
 
 

 
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
      
        
        ../verilog/sim/top
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.syn
        verilogSourcefragment
      
 
      
        
        ../verilog/syn/top
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="micro_bus_model"
                                   spirit:version="def.design"/>
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

 
addr_width
16
 
OUT_DELAY
15
 
 
OUT_WIDTH
10
 

 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
addr
reg
out
150

 
wdata
reg
out
70

 
rd
reg
out

 
wr
reg
out

 
rdata
wire
inout
70

 
 
cs
reg
out

 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus_model/] [rtl/] [xml/] [micro_bus_model_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`micro_bus_model`
40			`def default`
41
42
43
44
45
46
47
48			`mb`
49
50
51
52
53
54
55
56			`addr`
57
58			`addr`
59	133	jt_eaton	`addr_width-10`
60	131	jt_eaton
61
62
63
64			`wdata`
65
66			`wdata`
67			`70`
68
69
70
71
72			`rd`
73
74			`rd`
75
76
77
78
79
80			`wr`
81
82			`wr`
83
84
85
86
87
88			`cs`
89
90			`cs`
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107	133	jt_eaton
108	131	jt_eaton
109	133	jt_eaton	`elab_verilog`
110			`102.1`
111			`none`
112			`:Simulation:`
113			`./tools/verilog/elab_verilog`
114
115
116			`dest_dir`
117			`io_ports`
118
119
120
121
122
123
124
125
126			`gen_verilog_sim`
127			`104.0`
128			`none`
129			`:Simulation:`
130			`./tools/verilog/gen_verilog`
131
132
133			`destination`
134			`top`
135
136
137			`dest_dir`
138			`../verilog`
139
140
141
142
143
144
145
146
147			`gen_verilog_syn`
148			`104.0`
149			`none`
150			`:Synthesis:`
151			`./tools/verilog/gen_verilog`
152
153
154			`destination`
155			`top`
156
157
158			`dest_dir`
159			`../verilog`
160
161
162
163
164
165
166
167
168
169
170	131	jt_eaton	`gen_verilogLib_sim`
171			`105.0`
172			`none`
173			`:Simulation:`
174			`./tools/verilog/gen_verilogLib`
175
176
177			`dest_dir`
178			`../views`
179
180
181			`view`
182			`sim`
183
184
185
186
187
188			`gen_verilogLib_syn`
189			`105.0`
190			`none`
191			`:Synthesis:`
192			`./tools/verilog/gen_verilogLib`
193
194
195			`dest_dir`
196			`../views`
197
198
199			`view`
200			`syn`
201
202
203
204
205
206
207
208
209
210
211
212
213			`fs-sim`
214
215
216
217			`../verilog/copyright.v`
218			`verilogSourceinclude`
219
220
221
222
223			`../verilog/top.sim`
224	133	jt_eaton	`verilogSourcefragment`
225
226
227
228
229			`../verilog/sim/top`
230	131	jt_eaton	`verilogSourcemodule`
231
232
233
234			`dest_dir../views/sim/`
235			`verilogSourcelibraryDir`
236
237
238
239
240
241
242
243
244
245
246			`fs-syn`
247
248
249
250			`../verilog/copyright.v`
251			`verilogSourceinclude`
252
253
254
255
256			`../verilog/top.syn`
257	133	jt_eaton	`verilogSourcefragment`
258
259
260
261
262			`../verilog/syn/top`
263	131	jt_eaton	`verilogSourcemodule`
264
265
266	133	jt_eaton
267
268
269	131	jt_eaton
270			`dest_dir../views/syn/`
271			`verilogSourcelibraryDir`
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287			`Hierarchical`
288
289
290			`spirit:library="Testbench"`
291	133	jt_eaton	`spirit:name="micro_bus_model"`
292			`spirit:version="def.design"/>`
293	131	jt_eaton
294
295
296			`sim:Simulation:`
297
298			`Verilog`
299
300
301			`fs-sim`
302
303
304
305
306			`syn:Synthesis:`
307
308			`Verilog`
309
310
311			`fs-syn`
312
313
314
315
316
317			`doc`
318
319
320			`spirit:library="Testbench"`
321			`spirit:name="toolflow"`
322			`spirit:version="documentation"/>`
323
324			`:Documentation:`
325			`Verilog`
326
327
328
329
330
331
332
333
334			`addr_width`
335			`16`
336
337			`OUT_DELAY`
338			`15`
339
340
341			`OUT_WIDTH`
342			`10`
343
344
345
346
347
348
349
350
351
352			`clk`
353			`wire`
354			`in`
355
356
357			`reset`
358			`wire`
359			`in`
360
361
362			`addr`
363			`reg`
364			`out`
365			`150`
366
367
368			`wdata`
369			`reg`
370			`out`
371			`70`
372
373
374			`rd`
375			`reg`
376			`out`
377
378
379			`wr`
380			`reg`
381			`out`
382
383
384			`rdata`
385			`wire`
386			`inout`
387			`70`
388
389
390
391			`cs`
392	133	jt_eaton	`reg`
393	131	jt_eaton	`out`
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
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