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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [mt45w8mw12/] [rtl/] [verilog/] [top.syn] - Blame information for rev 134

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reg [7:0]                     memoryl [1<<MEM_BITS-1:0];
reg [7:0]                     memoryu [1<<MEM_BITS-1:0];
 
reg [DQ_BITS-1 : 0]           dq_out;
 
 
// Write Memory
 
 
 
 
// Read Memory
 
always@(*)      dq_out[7:0]  = 8'h0;
always@(*)      dq_out[15:8] = 8'h0;
 
// Tristate output
 
// assign  dq    =  (!ce_n && !oe_n) ? dq_out[DQ_BITS-1:0]: {DQ_BITS{1'bz}};
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`reg [7:0] memoryl [1<<MEM_BITS-1:0];`
3			`reg [7:0] memoryu [1<<MEM_BITS-1:0];`
4
5			`reg [DQ_BITS-1 : 0] dq_out;`
6
7
8			`// Write Memory`
9
10
11
12
13			`// Read Memory`
14
15			`always@(*) dq_out[7:0] = 8'h0;`
16			`always@(*) dq_out[15:8] = 8'h0;`
17
18			`// Tristate output`
19
20			`// assign dq = (!ce_n && !oe_n) ? dq_out[DQ_BITS-1:0]: {DQ_BITS{1'bz}};`
21
22
23

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [mt45w8mw12/] [rtl/] [verilog/] [top.syn] - Blame information for rev 134