URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [mt45w8mw12/] [rtl/] [xml/] [mt45w8mw12_def.xml] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
mt45w8mw12
def  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      mt45w8mw12_def
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      mt45w8mw12_def
    
  

 
 

 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

ADDR_BITS23
DQ_BITS16
MEM_BITS16

 

 
clk
wire
in

 
adv_n
wire
in

 
cre
wire
in

 
o_wait
wire
out

 
 
ce_n
wire
in

 
 
oe_n
wire
in

 
we_n
wire
in

 
 
lb_n
wire
in

 
ub_n
wire
in

 
addr
wire
in
ADDR_BITS-10

 
 
dq
wire
inout
DQ_BITS-10

 
 

 

 
 
 
 
 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
      
        
        ../verilog/sim/mt45w8mw12_def
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/top.syn
        verilogSourcefragment
      
 
 
      
        
        ../verilog/syn/mt45w8mw12_def
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
  
 
 
 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [mt45w8mw12/] [rtl/] [xml/] [mt45w8mw12_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`mt45w8mw12`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51	134	jt_eaton	`gen_verilog_sim`
52			`104.0`
53	131	jt_eaton	`none`
54			`:Simulation:`
55	134	jt_eaton	`./tools/verilog/gen_verilog`
56	131	jt_eaton
57
58	134	jt_eaton	`destination`
59			`mt45w8mw12_def`
60	131	jt_eaton
61	134	jt_eaton
62	131	jt_eaton
63
64
65
66	134	jt_eaton	`gen_verilog_syn`
67			`104.0`
68	131	jt_eaton	`none`
69			`:Synthesis:`
70	134	jt_eaton	`./tools/verilog/gen_verilog`
71	131	jt_eaton
72
73	134	jt_eaton	`destination`
74			`mt45w8mw12_def`
75	131	jt_eaton
76	134	jt_eaton
77	131	jt_eaton
78
79
80
81
82
83
84
85
86	134	jt_eaton
87
88	131	jt_eaton
89
90	134	jt_eaton
91			`verilog`
92
93
94			`spirit:library="Testbench"`
95			`spirit:name="toolflow"`
96			`spirit:version="verilog"/>`
97
98
99	131	jt_eaton
100
101
102
103			`sim:Simulation:`
104
105			`Verilog`
106
107
108			`fs-sim`
109
110
111
112
113			`syn:Synthesis:`
114
115			`Verilog`
116
117
118			`fs-syn`
119
120
121
122
123
124			`doc`
125
126
127			`spirit:library="Testbench"`
128			`spirit:name="toolflow"`
129			`spirit:version="documentation"/>`
130
131			`:Documentation:`
132			`Verilog`
133
134
135
136
137
138
139
140			`ADDR_BITS23`
141			`DQ_BITS16`
142			`MEM_BITS16`
143
144
145
146
147			`clk`
148			`wire`
149			`in`
150
151
152			`adv_n`
153			`wire`
154			`in`
155
156
157			`cre`
158			`wire`
159			`in`
160
161
162			`o_wait`
163			`wire`
164			`out`
165
166
167
168			`ce_n`
169			`wire`
170			`in`
171
172
173
174			`oe_n`
175			`wire`
176			`in`
177
178
179			`we_n`
180			`wire`
181			`in`
182
183
184
185			`lb_n`
186			`wire`
187			`in`
188
189
190			`ub_n`
191			`wire`
192			`in`
193
194
195			`addr`
196			`wire`
197			`in`
198			`ADDR_BITS-10`
199
200
201
202			`dq`
203			`wire`
204			`inout`
205			`DQ_BITS-10`
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220	134	jt_eaton
221	131	jt_eaton
222	134	jt_eaton
223			`fs-sim`
224	131	jt_eaton
225	134	jt_eaton
226
227			`../verilog/copyright`
228			`verilogSourceinclude`
229
230	131	jt_eaton
231	134	jt_eaton
232
233			`../verilog/top.sim`
234			`verilogSourcefragment`
235
236	131	jt_eaton
237
238	134	jt_eaton
239
240			`../verilog/sim/mt45w8mw12_def`
241			`verilogSourcemodule`
242
243	131	jt_eaton
244	134	jt_eaton
245
246			`dest_dir../views/sim/`
247			`verilogSourcelibraryDir`
248
249
250
251
252
253
254
255
256
257			`fs-syn`
258
259
260
261			`../verilog/copyright`
262			`verilogSourceinclude`
263
264
265
266
267			`../verilog/top.syn`
268			`verilogSourcefragment`
269
270
271
272
273
274			`../verilog/syn/mt45w8mw12_def`
275			`verilogSourcemodule`
276
277
278
279			`dest_dir../views/syn/`
280			`verilogSourcelibraryDir`
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296	131	jt_eaton