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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [or1200_dbg_model/] [rtl/] [verilog/] [top.task] - Blame information for rev 131

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   reg [31:0]  exp_rdata;
   reg [31:0]  mask_rdata;
 
 
always@(posedge clk)
  if(reset)
    begin
      dbg_adr_i      <=  32'h00000000;
      dbg_dat_i      <=  32'h00000000;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b0;
      dbg_stall_i    <=  1'b1;
      dbg_ewt_i      <=  1'b0;
      exp_rdata      <=  32'h00000000;
      mask_rdata     <=  32'h00000000;
      end // if (reset)
 
 
 
 
 
io_probe_in
 #(.MESG         ("or1200 rdata Error"),
   .WIDTH        (32)
  )
rdata_tpb
  (
  .clk            (  clk        ),
  .expected_value (  exp_rdata  ),
  .mask           (  mask_rdata ),
  .signal         (  dbg_dat_o  )
  );
 
 
  // Tasks
 
 
 
task automatic next;
  input [31:0] num;
  repeat (num)       @ (posedge clk);
endtask // next
 
 
 
 
 
  // write cycle
  task u_write;
    input [31:0] a;
    input  [31:0] d;
 
    begin
 
      $display("%t %m cycle %x %x",$realtime,a,d );
 
      dbg_adr_i      <=  a;
      dbg_dat_i      <=  d;
      dbg_we_i       <=  1'b1;
      dbg_stb_i      <=  1'b1;
      next(1);
      dbg_adr_i      <=  32'h00000000;
      dbg_dat_i      <=  32'h00000000;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b0;
 
    end
  endtask
 
 
 
// read cycle
  task u_read;
    input   [31:0]  a;
    output  [31:0]   d;
 
     begin
 
      dbg_adr_i      <=  a;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b1;
      next(4);
      d              <= dbg_dat_o;
      $display("%t %m  cycle %x %x",$realtime,a,dbg_dat_o );
      next(1);
      dbg_adr_i      <=  32'h00000000;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b0;
      next(1);
    end
  endtask
 
 
 
 
 
// compare cycle
  task u_cmp;
    input   [31:0]  a;
    input  [31:0]   d_exp;
 
     begin
      dbg_adr_i      <=  a;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b1;
      exp_rdata      <=  d_exp;
      next(4);
      mask_rdata     <= 32'hffffffff;
      next(1);
      $display("%t %m  cycle %x %x",$realtime,a,d_exp );
      mask_rdata     <= 32'h00000000;
      next(1);
      dbg_adr_i      <=  32'h00000000;
      dbg_we_i       <=  1'b0;
      dbg_stb_i      <=  1'b0;
      next(1);
    end
  endtask
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`reg [31:0] exp_rdata;`
2			`reg [31:0] mask_rdata;`
3
4
5			`always@(posedge clk)`
6			`if(reset)`
7			`begin`
8			`dbg_adr_i <= 32'h00000000;`
9			`dbg_dat_i <= 32'h00000000;`
10			`dbg_we_i <= 1'b0;`
11			`dbg_stb_i <= 1'b0;`
12			`dbg_stall_i <= 1'b1;`
13			`dbg_ewt_i <= 1'b0;`
14			`exp_rdata <= 32'h00000000;`
15			`mask_rdata <= 32'h00000000;`
16			`end // if (reset)`
17
18
19
20
21
22			`io_probe_in`
23			`#(.MESG ("or1200 rdata Error"),`
24			`.WIDTH (32)`
25			`)`
26			`rdata_tpb`
27			`(`
28			`.clk ( clk ),`
29			`.expected_value ( exp_rdata ),`
30			`.mask ( mask_rdata ),`
31			`.signal ( dbg_dat_o )`
32			`);`
33
34
35			`// Tasks`
36
37
38
39			`task automatic next;`
40			`input [31:0] num;`
41			`repeat (num) @ (posedge clk);`
42			`endtask // next`
43
44
45
46
47
48			`// write cycle`
49			`task u_write;`
50			`input [31:0] a;`
51			`input [31:0] d;`
52
53			`begin`
54
55			`$display("%t %m cycle %x %x",$realtime,a,d );`
56
57			`dbg_adr_i <= a;`
58			`dbg_dat_i <= d;`
59			`dbg_we_i <= 1'b1;`
60			`dbg_stb_i <= 1'b1;`
61			`next(1);`
62			`dbg_adr_i <= 32'h00000000;`
63			`dbg_dat_i <= 32'h00000000;`
64			`dbg_we_i <= 1'b0;`
65			`dbg_stb_i <= 1'b0;`
66
67			`end`
68			`endtask`
69
70
71
72			`// read cycle`
73			`task u_read;`
74			`input [31:0] a;`
75			`output [31:0] d;`
76
77			`begin`
78
79			`dbg_adr_i <= a;`
80			`dbg_we_i <= 1'b0;`
81			`dbg_stb_i <= 1'b1;`
82			`next(4);`
83			`d <= dbg_dat_o;`
84			`$display("%t %m cycle %x %x",$realtime,a,dbg_dat_o );`
85			`next(1);`
86			`dbg_adr_i <= 32'h00000000;`
87			`dbg_we_i <= 1'b0;`
88			`dbg_stb_i <= 1'b0;`
89			`next(1);`
90			`end`
91			`endtask`
92
93
94
95
96
97			`// compare cycle`
98			`task u_cmp;`
99			`input [31:0] a;`
100			`input [31:0] d_exp;`
101
102			`begin`
103			`dbg_adr_i <= a;`
104			`dbg_we_i <= 1'b0;`
105			`dbg_stb_i <= 1'b1;`
106			`exp_rdata <= d_exp;`
107			`next(4);`
108			`mask_rdata <= 32'hffffffff;`
109			`next(1);`
110			`$display("%t %m cycle %x %x",$realtime,a,d_exp );`
111			`mask_rdata <= 32'h00000000;`
112			`next(1);`
113			`dbg_adr_i <= 32'h00000000;`
114			`dbg_we_i <= 1'b0;`
115			`dbg_stb_i <= 1'b0;`
116			`next(1);`
117			`end`
118			`endtask`
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [or1200_dbg_model/] [rtl/] [verilog/] [top.task] - Blame information for rev 131