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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_host/] [rtl/] [xml/] [ps2_host_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
ps2_host
def  default
 

 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 

 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.sim
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="io_probe"
                                   spirit:version="def.design"/>
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 

 
clk
wire
in

 
reset
wire
in

 
 
busy
wire
in

 
rx_read
wire
in

 
 
rx_full
wire
in

 
rx_parity_error
wire
in

 
rx_parity_rcv
wire
in

 
rx_parity_cal
wire
in

 
rx_frame_error
wire
in

 
rx_clr
wire
out

 
 
 
tx_write
wire
out

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_host/] [rtl/] [xml/] [ps2_host_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`ps2_host`
40			`def default`
41
42
43
44
45			`gen_verilogLib_sim`
46			`105.0`
47			`none`
48			`:Simulation:`
49			`./tools/verilog/gen_verilogLib`
50
51
52			`dest_dir`
53			`../views`
54
55
56			`view`
57			`sim`
58
59
60
61
62
63			`gen_verilogLib_syn`
64			`105.0`
65			`none`
66			`:Synthesis:`
67			`./tools/verilog/gen_verilogLib`
68
69
70			`dest_dir`
71			`../views`
72
73
74			`view`
75			`syn`
76
77
78
79
80
81
82
83
84
85
86
87			`fs-sim`
88
89
90
91			`../verilog/copyright.v`
92			`verilogSourceinclude`
93
94
95
96
97			`../verilog/top.sim`
98			`verilogSourcemodule`
99
100
101
102
103			`dest_dir../views/sim/`
104			`verilogSourcelibraryDir`
105
106
107
108
109
110
111			`fs-syn`
112
113
114
115			`../verilog/copyright.v`
116			`verilogSourceinclude`
117
118
119
120
121			`../verilog/top.syn`
122			`verilogSourcemodule`
123
124
125
126			`dest_dir../views/syn/`
127			`verilogSourcelibraryDir`
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146			`Hierarchical`
147
148
149			`spirit:library="Testbench"`
150			`spirit:name="io_probe"`
151			`spirit:version="def.design"/>`
152
153
154
155			`sim:Simulation:`
156
157			`Verilog`
158
159
160			`fs-sim`
161
162
163
164
165			`syn:Synthesis:`
166
167			`Verilog`
168
169
170			`fs-syn`
171
172
173
174
175
176			`doc`
177
178
179			`spirit:library="Testbench"`
180			`spirit:name="toolflow"`
181			`spirit:version="documentation"/>`
182
183			`:Documentation:`
184			`Verilog`
185
186
187
188
189
190
191
192			`clk`
193			`wire`
194			`in`
195
196
197			`reset`
198			`wire`
199			`in`
200
201
202
203			`busy`
204			`wire`
205			`in`
206
207
208			`rx_read`
209			`wire`
210			`in`
211
212
213
214			`rx_full`
215			`wire`
216			`in`
217
218
219			`rx_parity_error`
220			`wire`
221			`in`
222
223
224			`rx_parity_rcv`
225			`wire`
226			`in`
227
228
229			`rx_parity_cal`
230			`wire`
231			`in`
232
233
234			`rx_frame_error`
235			`wire`
236			`in`
237
238
239			`rx_clr`
240			`wire`
241			`out`
242
243
244
245
246			`tx_write`
247			`wire`
248			`out`
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
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