URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_host/] [rtl/] [xml/] [ps2_host_def.xml] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
ps2_host
def  default
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      ps2_host_def
    
  

 
 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
  
    
      destination
      ps2_host_def
    
  

 
 
 

 
 
 
 
 
 

       
 
 
             
              Hierarchical
              
                                   spirit:library="Testbench"
                                   spirit:name="ps2_host"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 

 
clk
wire
in

 
reset
wire
in

 
 
busy
wire
in

 
rx_read
wire
in

 
 
rx_full
wire
in

 
rx_parity_error
wire
in

 
rx_parity_rcv
wire
in

 
rx_parity_cal
wire
in

 
tx_ack_error
wire
in

 
rx_frame_error
wire
in

 
rx_clr
reg
out

 
tx_write
reg
out

 
 

tx_data
reg
out70

 
 

rx_data
wire
in70

 
 

 

 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/logic
        verilogSourcefragment
      
 
      
        
        ../verilog/tasks
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/ps2_host_def
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/logic
        verilogSourcefragment
      
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/ps2_host_def
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
  
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_host/] [rtl/] [xml/] [ps2_host_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`ps2_host`
40			`def default`
41
42
43
44	134	jt_eaton
45
46
47	131	jt_eaton
48	134	jt_eaton	`gen_verilog_sim`
49			`104.0`
50	131	jt_eaton	`none`
51			`:Simulation:`
52	134	jt_eaton	`./tools/verilog/gen_verilog`
53
54	131	jt_eaton
55	134	jt_eaton	`destination`
56			`ps2_host_def`
57	131	jt_eaton
58	134	jt_eaton
59	131	jt_eaton
60
61	134	jt_eaton
62
63	131	jt_eaton
64	134	jt_eaton	`gen_verilog_syn`
65			`104.0`
66	131	jt_eaton	`none`
67			`:Synthesis:`
68	134	jt_eaton	`./tools/verilog/gen_verilog`
69
70	131	jt_eaton
71	134	jt_eaton	`destination`
72			`ps2_host_def`
73	131	jt_eaton
74	134	jt_eaton
75	131	jt_eaton
76
77
78	134	jt_eaton
79	131	jt_eaton
80
81
82
83
84
85
86	134	jt_eaton
87
88	131	jt_eaton
89
90	134	jt_eaton
91			`Hierarchical`
92
93			`spirit:library="Testbench"`
94			`spirit:name="ps2_host"`
95			`spirit:version="def.design"/>`
96
97	131	jt_eaton
98
99	134	jt_eaton
100			`verilog`
101
102
103			`spirit:library="Testbench"`
104			`spirit:name="toolflow"`
105			`spirit:version="verilog"/>`
106
107
108	131	jt_eaton
109
110
111
112
113
114
115			`sim:Simulation:`
116			`Verilog`
117
118
119			`fs-sim`
120
121
122
123
124			`syn:Synthesis:`
125			`Verilog`
126
127
128			`fs-syn`
129
130
131
132
133
134			`doc`
135
136
137			`spirit:library="Testbench"`
138			`spirit:name="toolflow"`
139			`spirit:version="documentation"/>`
140
141			`:Documentation:`
142			`Verilog`
143
144
145
146
147
148
149
150			`clk`
151			`wire`
152			`in`
153
154
155			`reset`
156			`wire`
157			`in`
158
159
160
161			`busy`
162			`wire`
163			`in`
164
165
166			`rx_read`
167			`wire`
168			`in`
169
170
171
172			`rx_full`
173			`wire`
174			`in`
175
176
177			`rx_parity_error`
178			`wire`
179			`in`
180
181
182			`rx_parity_rcv`
183			`wire`
184			`in`
185
186
187			`rx_parity_cal`
188			`wire`
189			`in`
190
191
192	134	jt_eaton	`tx_ack_error`
193			`wire`
194			`in`
195
196
197	131	jt_eaton	`rx_frame_error`
198			`wire`
199			`in`
200
201
202			`rx_clr`
203	134	jt_eaton	`reg`
204	131	jt_eaton	`out`
205
206
207	134	jt_eaton	`tx_write`
208			`reg`
209			`out`
210
211	131	jt_eaton
212
213	134	jt_eaton
214			`tx_data`
215			`reg`
216			`out70`
217
218
219
220
221			`rx_data`
222	131	jt_eaton	`wire`
223	134	jt_eaton	`in70`
224	131	jt_eaton
225
226
227
228
229
230
231
232	134	jt_eaton
233	131	jt_eaton
234	134	jt_eaton
235			`fs-sim`
236	131	jt_eaton
237	134	jt_eaton
238
239			`../verilog/logic`
240			`verilogSourcefragment`
241
242	131	jt_eaton
243	134	jt_eaton
244
245			`../verilog/tasks`
246			`verilogSourcefragment`
247
248	131	jt_eaton
249
250	134	jt_eaton
251
252			`../verilog/copyright`
253			`verilogSourceinclude`
254
255	131	jt_eaton
256	134	jt_eaton
257
258			`../verilog/sim/ps2_host_def`
259			`verilogSourcemodule`
260
261	131	jt_eaton
262
263	134	jt_eaton
264			`dest_dir../views/sim/`
265			`verilogSourcelibraryDir`
266
267	131	jt_eaton
268	134	jt_eaton
269
270
271
272			`fs-syn`
273
274
275
276			`../verilog/logic`
277			`verilogSourcefragment`
278
279
280
281
282			`../verilog/copyright`
283			`verilogSourceinclude`
284
285
286
287
288			`../verilog/syn/ps2_host_def`
289			`verilogSourcemodule`
290
291
292
293			`dest_dir../views/syn/`
294			`verilogSourcelibraryDir`
295
296
297
298
299
300
301
302
303
304
305
306
307	131	jt_eaton