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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_model/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 131

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//********************************************************************
//*** TAP Controller State Machine
//********************************************************************
 
// TAP state parameters
parameter RESET            = 2'b00,
          WAIT_63US        = 2'b01,
          CLOCK            = 2'b10,
          IDLE             = 2'b11;
 
 
 
reg        device_rx_parity;
reg [7:0]  device_rx_data;
 
wire        prb_device_rx_parity;
wire [7:0]  prb_device_rx_data;
 
wire       device_rx_read;
reg        ps2_data_out;
reg        dev_host;
reg [1:0]  tap_state, next_tap_state;
reg [SIZE-1:0]  count;
reg        clk_out;
reg [4:0]  bit_cnt;
reg        ack;
reg [10:0] frame;
reg        clk_fall;
reg        clk_rise;
reg        device_write;
reg [7:0]  device_tx_data;
reg        device_tx_parity;
reg        device_ack;
reg        device_stop;
reg [7:0]  exp_device_rx_data;
reg [7:0]  mask_device_rx_data;
reg        exp_device_rx_parity;
reg        mask_device_rx_parity;
 
 
 
 
 
 
assign    prb_device_rx_parity = device_rx_parity;
assign    prb_device_rx_data   = device_rx_data;
 
 
 
 
 
 
 
io_probe_def
#(.MESG     ( "ps2 data receive error"),
  .WIDTH    ( 8))
device_rx_data_tpb (
   .clk            (  clk                 ),
   .drive_value    (8'bzzzzzzzz           ),
   .expected_value (  exp_device_rx_data  ),
   .mask           (  mask_device_rx_data ),
   .signal         (  prb_device_rx_data  )
 );
 
 
 
 
 
io_probe_def
#(.MESG     ( "ps2 parity receive error"))
device_rx_parity_tpb (
   .clk            (  clk                   ),
   .drive_value    (1'bz                    ),
   .expected_value (  exp_device_rx_parity  ),
   .mask           (  mask_device_rx_parity ),
   .signal         (  prb_device_rx_parity  )
 );
 
 
 
 
assign   ps2_clk  = clk_out ? 1'b0 : 1'bz  ;
assign   ps2_data = ps2_data_out ? 1'b0 : 1'bz  ;
 
 
 
 
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
    if (reset)
    begin
    tap_state <=  RESET;
    ps2_data_out <=  1'b0;
    end
    else
    begin
    tap_state  <=  next_tap_state;
    ps2_data_out <=  (  (tap_state == CLOCK) &&    (dev_host?  frame[0] : ack)           );
    end
  end
 
 
 
always @(posedge clk  or posedge reset )
  begin
    if (reset)                    dev_host <=  1'b0;
    else
    if( device_write)                     dev_host <=  1'b1;
    else
    if( bit_cnt == 5'h16  )       dev_host <=  1'b0;
    else                          dev_host <=  dev_host ;
  end
 
 
 
always@(*) ack =  (((bit_cnt == 5'h14)||  (bit_cnt == 5'h15)) && device_ack )   ;
 
 
 
 
// next state decode for tap controller
always @(*)
  begin
  if(device_write)    next_tap_state    =  CLOCK;
    else
    case (tap_state)    // synopsys parallel_case
      RESET:
            begin
            next_tap_state    =   ps2_clk  ? RESET : WAIT_63US ;
            end
 
      WAIT_63US:
            begin
            next_tap_state    =   ps2_clk   ?  CLOCK : WAIT_63US ;
            end
 
      CLOCK:
            begin
            next_tap_state    =  ((bit_cnt == 5'h16)&& (count == 'h0))  ? IDLE  : CLOCK;
            end
 
      IDLE:
            begin
            next_tap_state    =   ps2_data    ? IDLE : WAIT_63US;
            end
    endcase
    end
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
    if (reset)
      begin
      count    <=  CLKCNT;
      clk_out  <=  1'b0;
      bit_cnt  <=  5'h00;
      clk_fall <=  1'b0;
      clk_rise <=  1'b0;
      end
    else
    if((next_tap_state != CLOCK))
      begin
      count    <=  CLKCNT;
      clk_out  <=  1'b0;
      bit_cnt  <=  5'h00;
      clk_fall <=  1'b0;
      clk_rise <=  1'b0;
      end
    else
    if((count == 'h0) )
      begin
      count     <=   CLKCNT;
      clk_out   <=  !clk_out;
      bit_cnt   <=   bit_cnt+5'b0001;
      clk_fall  <=  !clk_out;
      clk_rise  <=   clk_out;
      end
    else
      begin
      count     <=  count - 'h1;
      clk_out   <=  clk_out;
      bit_cnt   <=  bit_cnt;
      clk_fall  <=  1'b0;
      clk_rise  <=  1'b0;
      end
  end
 
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
    if (reset)
      begin
         frame <= {device_ack,10'h000};
      end
    else
     if(device_write)
      begin
         frame <= {!device_stop,device_tx_parity,~device_tx_data,1'b1};
      end
    else
     if((tap_state == WAIT_63US) || (tap_state == IDLE))
      begin
         frame <= {device_ack,10'h000};
      end
    else
     if((tap_state == CLOCK) &&  clk_fall  && !dev_host )          frame <= { ps2_data,frame[10:1]};
    else
     if((tap_state == CLOCK) &&  clk_rise  &&  dev_host )          frame <= { 1'b0,frame[10:1]};
    else        frame <= frame;
  end
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
    if (reset)
      begin
         device_rx_data   <= 8'h00;
         device_rx_parity <= 1'b0;
      end
     else
     if(tap_state == WAIT_63US)
      begin
         device_rx_data   <= 8'h00;
         device_rx_parity <= 1'b0;
      end
 
    else
      if((bit_cnt == 5'h12) && clk_rise)
      begin
         device_rx_data   <= frame[10:3];
         device_rx_parity <= ps2_data;
      end
      else
              begin
         device_rx_data   <= device_rx_data;
         device_rx_parity <= device_rx_parity;
      end
 
  end
 
 
 
assign device_rx_read    =  (bit_cnt == 5'h13) && !dev_host && clk_fall;
 
 

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_model/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3			`//********************************************************************`
4			`//*** TAP Controller State Machine`
5			`//********************************************************************`
6
7			`// TAP state parameters`
8			`parameter RESET = 2'b00,`
9			`WAIT_63US = 2'b01,`
10			`CLOCK = 2'b10,`
11			`IDLE = 2'b11;`
12
13
14
15			`reg device_rx_parity;`
16			`reg [7:0] device_rx_data;`
17
18			`wire prb_device_rx_parity;`
19			`wire [7:0] prb_device_rx_data;`
20
21			`wire device_rx_read;`
22			`reg ps2_data_out;`
23			`reg dev_host;`
24			`reg [1:0] tap_state, next_tap_state;`
25			`reg [SIZE-1:0] count;`
26			`reg clk_out;`
27			`reg [4:0] bit_cnt;`
28			`reg ack;`
29			`reg [10:0] frame;`
30			`reg clk_fall;`
31			`reg clk_rise;`
32			`reg device_write;`
33			`reg [7:0] device_tx_data;`
34			`reg device_tx_parity;`
35			`reg device_ack;`
36			`reg device_stop;`
37			`reg [7:0] exp_device_rx_data;`
38			`reg [7:0] mask_device_rx_data;`
39			`reg exp_device_rx_parity;`
40			`reg mask_device_rx_parity;`
41
42
43
44
45
46
47			`assign prb_device_rx_parity = device_rx_parity;`
48			`assign prb_device_rx_data = device_rx_data;`
49
50
51
52
53
54
55
56			`io_probe_def`
57			`#(.MESG ( "ps2 data receive error"),`
58			`.WIDTH ( 8))`
59			`device_rx_data_tpb (`
60			`.clk ( clk ),`
61			`.drive_value (8'bzzzzzzzz ),`
62			`.expected_value ( exp_device_rx_data ),`
63			`.mask ( mask_device_rx_data ),`
64			`.signal ( prb_device_rx_data )`
65			`);`
66
67
68
69
70
71			`io_probe_def`
72			`#(.MESG ( "ps2 parity receive error"))`
73			`device_rx_parity_tpb (`
74			`.clk ( clk ),`
75			`.drive_value (1'bz ),`
76			`.expected_value ( exp_device_rx_parity ),`
77			`.mask ( mask_device_rx_parity ),`
78			`.signal ( prb_device_rx_parity )`
79			`);`
80
81
82
83
84			`assign ps2_clk = clk_out ? 1'b0 : 1'bz ;`
85			`assign ps2_data = ps2_data_out ? 1'b0 : 1'bz ;`
86
87
88
89
90
91
92
93
94			`always @(posedge clk or posedge reset )`
95			`begin`
96			`if (reset)`
97			`begin`
98			`tap_state <= RESET;`
99			`ps2_data_out <= 1'b0;`
100			`end`
101			`else`
102			`begin`
103			`tap_state <= next_tap_state;`
104			`ps2_data_out <= ( (tap_state == CLOCK) && (dev_host? frame[0] : ack) );`
105			`end`
106			`end`
107
108
109
110			`always @(posedge clk or posedge reset )`
111			`begin`
112			`if (reset) dev_host <= 1'b0;`
113			`else`
114			`if( device_write) dev_host <= 1'b1;`
115			`else`
116			`if( bit_cnt == 5'h16 ) dev_host <= 1'b0;`
117			`else dev_host <= dev_host ;`
118			`end`
119
120
121
122			`always@(*) ack = (((bit_cnt == 5'h14)\|\| (bit_cnt == 5'h15)) && device_ack ) ;`
123
124
125
126
127			`// next state decode for tap controller`
128			`always @(*)`
129			`begin`
130			`if(device_write) next_tap_state = CLOCK;`
131			`else`
132			`case (tap_state) // synopsys parallel_case`
133			`RESET:`
134			`begin`
135			`next_tap_state = ps2_clk ? RESET : WAIT_63US ;`
136			`end`
137
138			`WAIT_63US:`
139			`begin`
140			`next_tap_state = ps2_clk ? CLOCK : WAIT_63US ;`
141			`end`
142
143			`CLOCK:`
144			`begin`
145			`next_tap_state = ((bit_cnt == 5'h16)&& (count == 'h0)) ? IDLE : CLOCK;`
146			`end`
147
148			`IDLE:`
149			`begin`
150			`next_tap_state = ps2_data ? IDLE : WAIT_63US;`
151			`end`
152			`endcase`
153			`end`
154
155
156
157
158			`always @(posedge clk or posedge reset )`
159			`begin`
160			`if (reset)`
161			`begin`
162			`count <= CLKCNT;`
163			`clk_out <= 1'b0;`
164			`bit_cnt <= 5'h00;`
165			`clk_fall <= 1'b0;`
166			`clk_rise <= 1'b0;`
167			`end`
168			`else`
169			`if((next_tap_state != CLOCK))`
170			`begin`
171			`count <= CLKCNT;`
172			`clk_out <= 1'b0;`
173			`bit_cnt <= 5'h00;`
174			`clk_fall <= 1'b0;`
175			`clk_rise <= 1'b0;`
176			`end`
177			`else`
178			`if((count == 'h0) )`
179			`begin`
180			`count <= CLKCNT;`
181			`clk_out <= !clk_out;`
182			`bit_cnt <= bit_cnt+5'b0001;`
183			`clk_fall <= !clk_out;`
184			`clk_rise <= clk_out;`
185			`end`
186			`else`
187			`begin`
188			`count <= count - 'h1;`
189			`clk_out <= clk_out;`
190			`bit_cnt <= bit_cnt;`
191			`clk_fall <= 1'b0;`
192			`clk_rise <= 1'b0;`
193			`end`
194			`end`
195
196
197
198
199
200			`always @(posedge clk or posedge reset )`
201			`begin`
202			`if (reset)`
203			`begin`
204			`frame <= {device_ack,10'h000};`
205			`end`
206			`else`
207			`if(device_write)`
208			`begin`
209			`frame <= {!device_stop,device_tx_parity,~device_tx_data,1'b1};`
210			`end`
211			`else`
212			`if((tap_state == WAIT_63US) \|\| (tap_state == IDLE))`
213			`begin`
214			`frame <= {device_ack,10'h000};`
215			`end`
216			`else`
217			`if((tap_state == CLOCK) && clk_fall && !dev_host ) frame <= { ps2_data,frame[10:1]};`
218			`else`
219			`if((tap_state == CLOCK) && clk_rise && dev_host ) frame <= { 1'b0,frame[10:1]};`
220			`else frame <= frame;`
221			`end`
222
223
224
225
226			`always @(posedge clk or posedge reset )`
227			`begin`
228			`if (reset)`
229			`begin`
230			`device_rx_data <= 8'h00;`
231			`device_rx_parity <= 1'b0;`
232			`end`
233			`else`
234			`if(tap_state == WAIT_63US)`
235			`begin`
236			`device_rx_data <= 8'h00;`
237			`device_rx_parity <= 1'b0;`
238			`end`
239
240			`else`
241			`if((bit_cnt == 5'h12) && clk_rise)`
242			`begin`
243			`device_rx_data <= frame[10:3];`
244			`device_rx_parity <= ps2_data;`
245			`end`
246			`else`
247			`begin`
248			`device_rx_data <= device_rx_data;`
249			`device_rx_parity <= device_rx_parity;`
250			`end`
251
252			`end`
253
254
255
256			`assign device_rx_read = (bit_cnt == 5'h13) && !dev_host && clk_fall;`
257
258