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//********************************************************************
//*** TAP Controller State Machine
//********************************************************************
 
// TAP state parameters
parameter RESET            = 2'b00,
          WAIT_63US        = 2'b01,
          CLOCK            = 2'b10,
          IDLE             = 2'b11;
 
 
 
reg        device_rx_parity;
reg [7:0]  device_rx_data;
 
 
 
 
wire       device_rx_read;
reg        ps2_data_out;
reg        dev_host;
reg [1:0]  tap_state, next_tap_state;
reg [SIZE-1:0]  count;
reg        clk_out;
reg [4:0]  bit_cnt;
reg        ack;
reg [10:0] frame;
reg        clk_fall;
reg        clk_rise;
reg        device_write;
reg [7:0]  device_tx_data;
reg        device_tx_parity;
reg        device_ack;
reg        device_stop;
 
 
 
 
 
assign    drv_device_rx_data   = 8'bzzzzzzzz;
assign    prb_device_rx_parity = device_rx_parity;
assign    prb_device_rx_data   = device_rx_data;
 
 
assign    drv_device_rx_parity = 1'bz;
 
 
/*
 
io_probe_def
#(.MESG     ( "ps2 data receive error"),
  .WIDTH    ( 8))
device_rx_data_tpb (
   .clk            (  clk                 ),
   .drive_value    (  drv_device_rx_data  ),
   .expected_value (  exp_device_rx_data  ),
   .mask           (  mask_device_rx_data ),
   .signal         (  prb_device_rx_data  )
 );
 
 
 
 
 
io_probe_def
#(.MESG     ( "ps2 parity receive error"))
device_rx_parity_tpb (
   .clk            (  clk                   ),
   .drive_value    (  drv_device_rx_parity  ),
   .expected_value (  exp_device_rx_parity  ),
   .mask           (  mask_device_rx_parity ),
   .signal         (  prb_device_rx_parity  )
 );
 
*/
 
 
assign   ps2_clk  = clk_out ? 1'b0 : 1'bz  ;
assign   ps2_data = ps2_data_out ? 1'b0 : 1'bz  ;
 
 
 
 
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
    if (reset)
    begin
    tap_state <=  RESET;
    ps2_data_out <=  1'b0;
    end
    else
    begin
    tap_state  <=  next_tap_state;
    ps2_data_out <=  (  (tap_state == CLOCK) &&    (dev_host?  frame[0] : ack)           );
    end
  end
 
 
 
always @(posedge clk  or posedge reset )
  begin
    if (reset)                    dev_host <=  1'b0;
    else
    if( device_write)                     dev_host <=  1'b1;
    else
    if( bit_cnt == 5'h16  )       dev_host <=  1'b0;
    else                          dev_host <=  dev_host ;
  end
 
 
 
always@(*) ack =  (((bit_cnt == 5'h14)||  (bit_cnt == 5'h15)) && device_ack )   ;
 
 
 
 
// next state decode for tap controller
always @(*)
  begin
  if(device_write)    next_tap_state    =  CLOCK;
    else
    case (tap_state)    // synopsys parallel_case
      RESET:
            begin
            next_tap_state    =   ps2_clk  ? RESET : WAIT_63US ;
            end
 
      WAIT_63US:
            begin
            next_tap_state    =   ps2_clk   ?  CLOCK : WAIT_63US ;
            end
 
      CLOCK:
            begin
            next_tap_state    =  ((bit_cnt == 5'h16)&& (count == 'h0))  ? IDLE  : CLOCK;
            end
 
      IDLE:
            begin
            next_tap_state    =   ps2_data    ? IDLE : WAIT_63US;
            end
    endcase
    end
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
    if (reset)
      begin
      count    <=  CLKCNT;
      clk_out  <=  1'b0;
      bit_cnt  <=  5'h00;
      clk_fall <=  1'b0;
      clk_rise <=  1'b0;
      end
    else
    if((next_tap_state != CLOCK))
      begin
      count    <=  CLKCNT;
      clk_out  <=  1'b0;
      bit_cnt  <=  5'h00;
      clk_fall <=  1'b0;
      clk_rise <=  1'b0;
      end
    else
    if((count == 'h0) )
      begin
      count     <=   CLKCNT;
      clk_out   <=  !clk_out;
      bit_cnt   <=   bit_cnt+5'b0001;
      clk_fall  <=  !clk_out;
      clk_rise  <=   clk_out;
      end
    else
      begin
      count     <=  count - 'h1;
      clk_out   <=  clk_out;
      bit_cnt   <=  bit_cnt;
      clk_fall  <=  1'b0;
      clk_rise  <=  1'b0;
      end
  end
 
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
    if (reset)
      begin
         frame <= {device_ack,10'h000};
      end
    else
     if(device_write)
      begin
         frame <= {!device_stop,device_tx_parity,~device_tx_data,1'b1};
      end
    else
     if((tap_state == WAIT_63US) || (tap_state == IDLE))
      begin
         frame <= {device_ack,10'h000};
      end
    else
     if((tap_state == CLOCK) &&  clk_fall  && !dev_host )          frame <= { ps2_data,frame[10:1]};
    else
     if((tap_state == CLOCK) &&  clk_rise  &&  dev_host )          frame <= { 1'b0,frame[10:1]};
    else        frame <= frame;
  end
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
    if (reset)
      begin
         device_rx_data   <= 8'h00;
         device_rx_parity <= 1'b0;
      end
     else
     if(tap_state == WAIT_63US)
      begin
         device_rx_data   <= 8'h00;
         device_rx_parity <= 1'b0;
      end
 
    else
      if((bit_cnt == 5'h12) && clk_rise)
      begin
         device_rx_data   <= frame[10:3];
         device_rx_parity <= ps2_data;
      end
      else
              begin
         device_rx_data   <= device_rx_data;
         device_rx_parity <= device_rx_parity;
      end
 
  end
 
 
 
assign device_rx_read    =  (bit_cnt == 5'h13) && !dev_host && clk_fall;
 
 

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_model/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3			`//********************************************************************`
4			`//*** TAP Controller State Machine`
5			`//********************************************************************`
6
7			`// TAP state parameters`
8			`parameter RESET = 2'b00,`
9			`WAIT_63US = 2'b01,`
10			`CLOCK = 2'b10,`
11			`IDLE = 2'b11;`
12
13
14
15			`reg device_rx_parity;`
16			`reg [7:0] device_rx_data;`
17
18	133	jt_eaton
19
20	131	jt_eaton
21			`wire device_rx_read;`
22			`reg ps2_data_out;`
23			`reg dev_host;`
24			`reg [1:0] tap_state, next_tap_state;`
25			`reg [SIZE-1:0] count;`
26			`reg clk_out;`
27			`reg [4:0] bit_cnt;`
28			`reg ack;`
29			`reg [10:0] frame;`
30			`reg clk_fall;`
31			`reg clk_rise;`
32			`reg device_write;`
33			`reg [7:0] device_tx_data;`
34			`reg device_tx_parity;`
35			`reg device_ack;`
36			`reg device_stop;`
37
38
39
40
41
42	133	jt_eaton	`assign drv_device_rx_data = 8'bzzzzzzzz;`
43	131	jt_eaton	`assign prb_device_rx_parity = device_rx_parity;`
44			`assign prb_device_rx_data = device_rx_data;`
45
46
47	133	jt_eaton	`assign drv_device_rx_parity = 1'bz;`
48	131	jt_eaton
49
50	133	jt_eaton	`/*`
51	131	jt_eaton
52			`io_probe_def`
53			`#(.MESG ( "ps2 data receive error"),`
54			`.WIDTH ( 8))`
55			`device_rx_data_tpb (`
56			`.clk ( clk ),`
57	133	jt_eaton	`.drive_value ( drv_device_rx_data ),`
58	131	jt_eaton	`.expected_value ( exp_device_rx_data ),`
59			`.mask ( mask_device_rx_data ),`
60			`.signal ( prb_device_rx_data )`
61			`);`
62
63
64
65
66
67			`io_probe_def`
68			`#(.MESG ( "ps2 parity receive error"))`
69			`device_rx_parity_tpb (`
70			`.clk ( clk ),`
71	133	jt_eaton	`.drive_value ( drv_device_rx_parity ),`
72	131	jt_eaton	`.expected_value ( exp_device_rx_parity ),`
73			`.mask ( mask_device_rx_parity ),`
74			`.signal ( prb_device_rx_parity )`
75			`);`
76
77	133	jt_eaton	`*/`
78	131	jt_eaton
79
80			`assign ps2_clk = clk_out ? 1'b0 : 1'bz ;`
81			`assign ps2_data = ps2_data_out ? 1'b0 : 1'bz ;`
82
83
84
85
86
87
88
89
90			`always @(posedge clk or posedge reset )`
91			`begin`
92			`if (reset)`
93			`begin`
94			`tap_state <= RESET;`
95			`ps2_data_out <= 1'b0;`
96			`end`
97			`else`
98			`begin`
99			`tap_state <= next_tap_state;`
100			`ps2_data_out <= ( (tap_state == CLOCK) && (dev_host? frame[0] : ack) );`
101			`end`
102			`end`
103
104
105
106			`always @(posedge clk or posedge reset )`
107			`begin`
108			`if (reset) dev_host <= 1'b0;`
109			`else`
110			`if( device_write) dev_host <= 1'b1;`
111			`else`
112			`if( bit_cnt == 5'h16 ) dev_host <= 1'b0;`
113			`else dev_host <= dev_host ;`
114			`end`
115
116
117
118			`always@(*) ack = (((bit_cnt == 5'h14)\|\| (bit_cnt == 5'h15)) && device_ack ) ;`
119
120
121
122
123			`// next state decode for tap controller`
124			`always @(*)`
125			`begin`
126			`if(device_write) next_tap_state = CLOCK;`
127			`else`
128			`case (tap_state) // synopsys parallel_case`
129			`RESET:`
130			`begin`
131			`next_tap_state = ps2_clk ? RESET : WAIT_63US ;`
132			`end`
133
134			`WAIT_63US:`
135			`begin`
136			`next_tap_state = ps2_clk ? CLOCK : WAIT_63US ;`
137			`end`
138
139			`CLOCK:`
140			`begin`
141			`next_tap_state = ((bit_cnt == 5'h16)&& (count == 'h0)) ? IDLE : CLOCK;`
142			`end`
143
144			`IDLE:`
145			`begin`
146			`next_tap_state = ps2_data ? IDLE : WAIT_63US;`
147			`end`
148			`endcase`
149			`end`
150
151
152
153
154			`always @(posedge clk or posedge reset )`
155			`begin`
156			`if (reset)`
157			`begin`
158			`count <= CLKCNT;`
159			`clk_out <= 1'b0;`
160			`bit_cnt <= 5'h00;`
161			`clk_fall <= 1'b0;`
162			`clk_rise <= 1'b0;`
163			`end`
164			`else`
165			`if((next_tap_state != CLOCK))`
166			`begin`
167			`count <= CLKCNT;`
168			`clk_out <= 1'b0;`
169			`bit_cnt <= 5'h00;`
170			`clk_fall <= 1'b0;`
171			`clk_rise <= 1'b0;`
172			`end`
173			`else`
174			`if((count == 'h0) )`
175			`begin`
176			`count <= CLKCNT;`
177			`clk_out <= !clk_out;`
178			`bit_cnt <= bit_cnt+5'b0001;`
179			`clk_fall <= !clk_out;`
180			`clk_rise <= clk_out;`
181			`end`
182			`else`
183			`begin`
184			`count <= count - 'h1;`
185			`clk_out <= clk_out;`
186			`bit_cnt <= bit_cnt;`
187			`clk_fall <= 1'b0;`
188			`clk_rise <= 1'b0;`
189			`end`
190			`end`
191
192
193
194
195
196			`always @(posedge clk or posedge reset )`
197			`begin`
198			`if (reset)`
199			`begin`
200			`frame <= {device_ack,10'h000};`
201			`end`
202			`else`
203			`if(device_write)`
204			`begin`
205			`frame <= {!device_stop,device_tx_parity,~device_tx_data,1'b1};`
206			`end`
207			`else`
208			`if((tap_state == WAIT_63US) \|\| (tap_state == IDLE))`
209			`begin`
210			`frame <= {device_ack,10'h000};`
211			`end`
212			`else`
213			`if((tap_state == CLOCK) && clk_fall && !dev_host ) frame <= { ps2_data,frame[10:1]};`
214			`else`
215			`if((tap_state == CLOCK) && clk_rise && dev_host ) frame <= { 1'b0,frame[10:1]};`
216			`else frame <= frame;`
217			`end`
218
219
220
221
222			`always @(posedge clk or posedge reset )`
223			`begin`
224			`if (reset)`
225			`begin`
226			`device_rx_data <= 8'h00;`
227			`device_rx_parity <= 1'b0;`
228			`end`
229			`else`
230			`if(tap_state == WAIT_63US)`
231			`begin`
232			`device_rx_data <= 8'h00;`
233			`device_rx_parity <= 1'b0;`
234			`end`
235
236			`else`
237			`if((bit_cnt == 5'h12) && clk_rise)`
238			`begin`
239			`device_rx_data <= frame[10:3];`
240			`device_rx_parity <= ps2_data;`
241			`end`
242			`else`
243			`begin`
244			`device_rx_data <= device_rx_data;`
245			`device_rx_parity <= device_rx_parity;`
246			`end`
247
248			`end`
249
250
251
252			`assign device_rx_read = (bit_cnt == 5'h13) && !dev_host && clk_fall;`
253
254