URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_model/] [rtl/] [xml/] [ps2_model_def.xml] - Blame information for rev 131

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
ps2_model
def  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
      
        
        ../verilog/top.tasks
        verilogSourcefragment
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
 
 
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="io_probe"
                                   spirit:version="def.design"/>
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 

CLKCNT10'h1f0
SIZE10

 

 
clk
wire
in

 
reset
wire
in

 
 
ps2_clk
wire
inout

 
ps2_data
wire
inout

 

 

 
 
 
 
 
 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_model/] [rtl/] [xml/] [ps2_model_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`ps2_model`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog_sim`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59			`top.out.sim`
60
61
62			`dest_dir`
63			`../verilog`
64
65
66
67
68
69
70			`gen_verilog_syn`
71			`104.0`
72			`none`
73			`:Synthesis:`
74			`./tools/verilog/gen_verilog`
75
76
77			`destination`
78			`top.out.syn`
79
80
81			`dest_dir`
82			`../verilog`
83
84
85
86
87
88
89			`gen_verilogLib_sim`
90			`105.0`
91			`none`
92			`:Simulation:`
93			`./tools/verilog/gen_verilogLib`
94
95
96			`dest_dir`
97			`../views`
98
99
100			`view`
101			`sim`
102
103
104
105
106
107
108			`gen_verilogLib_syn`
109			`105.0`
110			`none`
111			`:Synthesis:`
112			`./tools/verilog/gen_verilogLib`
113
114
115			`dest_dir`
116			`../views`
117
118
119			`view`
120			`syn`
121
122
123
124
125
126
127
128
129
130
131
132
133			`fs-sim`
134
135
136
137			`../verilog/copyright.v`
138			`verilogSourceinclude`
139
140
141
142
143			`../verilog/sim/top.out.sim`
144			`verilogSourcemodule`
145
146
147
148
149
150			`../verilog/top.rtl`
151			`verilogSourcefragment`
152
153
154
155
156			`../verilog/top.tasks`
157			`verilogSourcefragment`
158
159
160
161			`dest_dir../views/sim/`
162			`verilogSourcelibraryDir`
163
164
165
166
167
168
169
170
171
172
173
174
175			`fs-syn`
176
177
178
179			`../verilog/copyright.v`
180			`verilogSourceinclude`
181
182
183
184
185
186			`../verilog/syn/top.out.syn`
187			`verilogSourcemodule`
188
189
190
191
192
193			`../verilog/top.rtl`
194			`verilogSourcefragment`
195
196
197
198			`dest_dir../views/syn/`
199			`verilogSourcelibraryDir`
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220			`Hierarchical`
221
222
223			`spirit:library="Testbench"`
224			`spirit:name="io_probe"`
225			`spirit:version="def.design"/>`
226
227
228
229			`sim:Simulation:`
230
231			`Verilog`
232
233
234			`fs-sim`
235
236
237
238
239			`syn:Synthesis:`
240
241			`Verilog`
242
243
244			`fs-syn`
245
246
247
248
249			`doc`
250
251
252			`spirit:library="Testbench"`
253			`spirit:name="toolflow"`
254			`spirit:version="documentation"/>`
255
256			`:Documentation:`
257			`Verilog`
258
259
260
261
262
263
264
265			`CLKCNT10'h1f0`
266			`SIZE10`
267
268
269
270
271			`clk`
272			`wire`
273			`in`
274
275
276			`reset`
277			`wire`
278			`in`
279
280
281
282			`ps2_clk`
283			`wire`
284			`inout`
285
286
287			`ps2_data`
288			`wire`
289			`inout`
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306