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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_model/] [rtl/] [xml/] [ps2_model_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
ps2_model
def  default
 
 
 
 
 
 
 


  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
      
        
        ../verilog/top.tasks
        verilogSourcefragment
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
 
 
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="ps2_model"
                                   spirit:version="def.design"/>
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 

CLKCNT10'h1f0
SIZE10

 

 
clk
wire
in

 
reset
wire
in

 
 
ps2_clk
wire
inout

 
ps2_data
wire
inout

 

 

 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_model/] [rtl/] [xml/] [ps2_model_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`ps2_model`
40			`def default`
41
42
43
44
45
46
47
48
49	133	jt_eaton
50			`elab_verilog`
51			`102.1`
52			`none`
53			`:Simulation:`
54			`./tools/verilog/elab_verilog`
55
56
57			`dest_dir`
58			`io_ports`
59
60
61
62	131	jt_eaton
63	133	jt_eaton
64
65	131	jt_eaton
66			`gen_verilog_sim`
67			`104.0`
68			`none`
69			`:Simulation:`
70			`./tools/verilog/gen_verilog`
71
72
73			`destination`
74			`top.out.sim`
75
76
77			`dest_dir`
78			`../verilog`
79
80
81
82
83
84
85			`gen_verilog_syn`
86			`104.0`
87			`none`
88			`:Synthesis:`
89			`./tools/verilog/gen_verilog`
90
91
92			`destination`
93			`top.out.syn`
94
95
96			`dest_dir`
97			`../verilog`
98
99
100
101
102
103
104			`gen_verilogLib_sim`
105			`105.0`
106			`none`
107			`:Simulation:`
108			`./tools/verilog/gen_verilogLib`
109
110
111			`dest_dir`
112			`../views`
113
114
115			`view`
116			`sim`
117
118
119
120
121
122
123			`gen_verilogLib_syn`
124			`105.0`
125			`none`
126			`:Synthesis:`
127			`./tools/verilog/gen_verilogLib`
128
129
130			`dest_dir`
131			`../views`
132
133
134			`view`
135			`syn`
136
137
138
139
140
141
142
143
144
145
146
147
148			`fs-sim`
149
150
151
152			`../verilog/copyright.v`
153			`verilogSourceinclude`
154
155
156
157
158			`../verilog/sim/top.out.sim`
159			`verilogSourcemodule`
160
161
162
163
164
165			`../verilog/top.rtl`
166			`verilogSourcefragment`
167
168
169
170
171			`../verilog/top.tasks`
172			`verilogSourcefragment`
173
174
175
176			`dest_dir../views/sim/`
177			`verilogSourcelibraryDir`
178
179
180
181
182
183
184
185
186
187
188
189
190			`fs-syn`
191
192
193
194			`../verilog/copyright.v`
195			`verilogSourceinclude`
196
197
198
199
200
201			`../verilog/syn/top.out.syn`
202			`verilogSourcemodule`
203
204
205
206
207
208			`../verilog/top.rtl`
209			`verilogSourcefragment`
210
211
212
213			`dest_dir../views/syn/`
214			`verilogSourcelibraryDir`
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235			`Hierarchical`
236
237
238			`spirit:library="Testbench"`
239	133	jt_eaton	`spirit:name="ps2_model"`
240	131	jt_eaton	`spirit:version="def.design"/>`
241
242
243
244			`sim:Simulation:`
245
246			`Verilog`
247
248
249			`fs-sim`
250
251
252
253
254			`syn:Synthesis:`
255
256			`Verilog`
257
258
259			`fs-syn`
260
261
262
263
264			`doc`
265
266
267			`spirit:library="Testbench"`
268			`spirit:name="toolflow"`
269			`spirit:version="documentation"/>`
270
271			`:Documentation:`
272			`Verilog`
273
274
275
276
277
278
279
280			`CLKCNT10'h1f0`
281			`SIZE10`
282
283
284
285
286			`clk`
287			`wire`
288			`in`
289
290
291			`reset`
292			`wire`
293			`in`
294
295
296
297			`ps2_clk`
298			`wire`
299			`inout`
300
301
302			`ps2_data`
303			`wire`
304			`inout`
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
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321