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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [spi_host/] [rtl/] [verilog/] [logic] - Blame information for rev 135

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always@(posedge clk)
  if(reset)
    begin
    tx_data              <= 8'h00;
    tx_write             <= 1'b0;
    rx_clr               <= 1'b0;
    exp_tx_ack_err       <= 1'b0;
    mask_tx_ack_err      <= 1'b0;
    exp_rcv_byte         <= 8'h00;
    mask_rcv_byte        <= 8'h00;
    end
 
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton	`always@(posedge clk)`
2			`if(reset)`
3			`begin`
4			`tx_data <= 8'h00;`
5			`tx_write <= 1'b0;`
6			`rx_clr <= 1'b0;`
7			`exp_tx_ack_err <= 1'b0;`
8			`mask_tx_ack_err <= 1'b0;`
9			`exp_rcv_byte <= 8'h00;`
10			`mask_rcv_byte <= 8'h00;`
11			`end`
12
13
14

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [spi_host/] [rtl/] [verilog/] [logic] - Blame information for rev 135